Demo Data from EDBT 2026 / reviewers in the wild / expert
Gordon K. Lin
dblp:38/800
· DBLP profile ↗
1ranked-venue papers
1as first author
0since 2021 · last 1983
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1 · 1 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Electronic design automation · 100% | |
| Theoretical computer science
1 paper |
Automata and formal languages · 100% |
Topics — the 5 heaviest of 5, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Electronic design automation › hardware verification and test › sequential circuit testing
checking experiments |
0.0 | 1 | 1983 | Totally Preset Checking Experiments for Sequential Machines · IEEE Trans. Computers 1983 |
Electronic design automation
hardware verification and test |
0.0 | 1 | 1983 | Totally Preset Checking Experiments for Sequential Machines · IEEE Trans. Computers 1983 |
Electronic design automation › hardware verification and test
sequential circuit testing |
0.0 | 1 | 1983 | Totally Preset Checking Experiments for Sequential Machines · IEEE Trans. Computers 1983 |
Automata and formal languages › finite automata
sequential machines |
0.0 | 1 | 1983 | Totally Preset Checking Experiments for Sequential Machines · IEEE Trans. Computers 1983 |
Automata and formal languages › finite automata › synchronizing automata
synchronizing sequences |
0.0 | 1 | 1983 | Totally Preset Checking Experiments for Sequential Machines · IEEE Trans. Computers 1983 |
Methods — techniques the papers use, named apart from their topics
checking sequence construction · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1983 | Totally Preset Checking Experiments for Sequential MachinesabstractIn this paper, we intoduce a new class of checking experiments, called uniform checking experiments, in which the entire input sequence, including the initialization part, is preset. The input sequence of a uniform checking experiment is called a uniform checking sequence. It is shown that every sequential machine possesses a uniform checking sequence. Trivially, if the machine has a synchronizing sequence, then the checking sequence constructed by employing any existent procedure is a uniform checking sequence. Some classes of machines which do not have synchronizing sequences are given and discussed. They are permutation machines, cycle machines, and symmetry machines. Different procedures for constructing efficient uniform checking sequences for them are then derived. It is found that while uniform checking sequences may be considerably longer than conventional checking sequences for arbitrary machines with no synchronizing sequences, the above classes of machines are shown to have uniform checking sequences comparable in length to conventional checking sequence. Gordon K. Lin, Prem R. Menon |
IEEE Trans. Computers | 1 |