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Timo Reis

dblp:38/8130 · DBLP profile ↗
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1ranked-venue papers
1as first author
0since 2021 · last 2010
—ORCID · unresolved

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 100%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation › circuit simulation › model order reduction
balanced truncation		 0.112010
PABTEC: Passivity-Preserving Balanced Truncation for Electrical Circuits · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2010
Electronic design automation
circuit simulation		 0.112010
PABTEC: Passivity-Preserving Balanced Truncation for Electrical Circuits · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2010
Electronic design automation › circuit simulation
model order reduction		 0.112010
PABTEC: Passivity-Preserving Balanced Truncation for Electrical Circuits · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2010
Electronic design automation › circuit simulation › reduced-order modeling
passivity preservation		 0.012010
PABTEC: Passivity-Preserving Balanced Truncation for Electrical Circuits · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2010

Methods — techniques the papers use, named apart from their topics

lur'e equations · 0.1balanced truncation · 0.1
YearPublicationVenuePosition
2010 PABTEC: Passivity-Preserving Balanced Truncation for Electrical Circuits
abstract
We present a passivity-preserving balanced truncation model reduction method for differential-algebraic equations arising in circuit simulation. This method is based on balancing the solutions of projected Lur'e equations. By making use of the special structure of circuit equations, we can reduce the numerical effort for balanced truncation significantly. It is shown that the property of reciprocity is also preserved in the reduced-order model. Network topological interpretations of certain circuit effects are given. The presented model reduction method is illustrated by numerical examples.
Timo Reis, Tatjana Stykel
 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.1