Message-passing-based inference algorithms have immense importance in real-world applications. In this paper, error resiliency of a message passing based Markov random field (MRF) stereo matching hardware is explored and enhanced through the application of statistical error compensation. Error resiliency is of particular interest for subnanometer and postsilicon devices. The inherent robustness of iteration-based MRF inference algorithms is explored and shows that small errors are tolerable, while large errors degrade the performance significantly. Based on these error characteristics, algorithmic noise tolerance (ANT) has been applied at the arithmetic, iteration, and system levels. Introducing timing errors via voltage overscaling, at the arithmetic level, results show that the ANT-based hardware can tolerate an error rate of 21.3%, with performance degradation of only 3.5% at an overhead of 97.4%, compared with an error-free hardware with an energy savings of 39.7%. To reduce compensation complexity, iteration and system-level compensation was explored. Results show that, compared with arithmetic level, system-level compensation reduces overhead to 59%, while maintaining stereo matching performance with only 2.5% degradation with 16% additional power savings. These results are verified via FPGA emulation with timing errors induced within the message passing unit via relaxed synthesis.

This paper presents an energy-efficient VLSI implementation of Sparse Distributed Memory (SDM). High throughput and energy-efficient Hamming distance-based address decoder (CM-DEC) is proposed by employing compute memory [1], where computation is deeply embedded into a memory (SRAM). Hierarchical binary decision (HBD) is also proposed to enhance area- and energy-efficiency of read operation by minimizing data transfer. The SDM is employed as an auto-associative memory with four read iterations and 16×16 binary noisy input image with input error rates of 15%, 25%, and 30%. The proposed SDM achieves 39× smaller energy delay product with 14.5× and 2.7× reduced delay and energy, respectively as compared to conventional digital implementation of SDM in 45 nm SOI CMOS process with output error rate degradation less than 0.4%.

In this brief, we present a novel architecture for pseudorandom (PN) code acquisition based on statistical error compensation (SEC), which achieves significant power savings. SEC treats errors in hardware as noise in communication networks, and employs robust estimation theory to compensate for errors. We apply SEC to a 256-tap PN code acquisition filter in a 180-nm CMOS process. Multiple (five) dies were tested under voltage overscaling to achieve a near constant detection probability (Pdet) above 90%. The minimum energy consumption ranged from 72.89 to 210.59 pJ (ave 122.52 pJ) for supply voltages between 0.69 and 0.70 V. These operating conditions result in raw error rates of 85.83%-91.23% (ave 88.99%). Energy savings over a conventional errorfree design ranges from 2.4× to 5.8× (ave 3.86×). Energy savings over past work ranges from 1.55× to 3.79× (ave 2.52×). Improvement in error-tolerance over existing error-tolerant designs range from 2146× to 2281× (ave 2225×). The large energy savings were found to be due to a combination of voltage scaling and activity factor reduction. The proposed design achieves a 2.5× improvement in the figure of merit [normalized power/(#taps * precision * sample rate)] compared with conventional PN code acquisition filters.

In this paper, we present an error resilient Markov random field (MRF) message passing based stereo matching hardware (HW) architecture. Previously, algorithmic noise tolerance (ANT) has been applied at the arithmetic level of the reparameterize unit and showed greatly enhanced robustness of message passing inference based architectures. In this work, correction was targeted at the system level to reduce correction overhead while maintaining performance. An erroneous FPGA based accelerator was employed as our emulation platform. Through relaxed synthesis, we show that timing errors occur within the message passing unit, and are successfully compensated. Error correction has been implemented at several hierarchical levels, including end of iteration, and the final depth map output. Significant enhancement in robustness is achieved with minimal correction overhead. Compared to HW error compensation at the arithmetic level, system level error compensation reduces overhead by more than 50 %, while maintaining stereo matching performance with only 3.8 % degradation.

In this paper, we present switched analog circuit (SAC), a new circuit architecture, to implement an energy-efficient mixed-signal dot product (DP) kernel for machine learning and signal processing applications. SAC operates by fast switching the analog inputs to output via variable width digital pulses. The output accuracy and energy consumption of SAC is analyzed and verified for an average and Gaussian blur filter. Simulations in a commercial 130 nm process for a 120 x 120 image show energy savings of 19x-to-32x compared to a digital implementation for signal-to-noise ratios (SNRs) of 30 dB-to-24 dB, respectively.

Algorithmic noise tolerance (ANT) is an effective statistical error compensation technique for digital signal processing systems. This paper proves a long held hypothesis that ANT has a strong Bayesian foundation, and develops an analytical framework for predicting the performance of, and designing performance-optimal ANT-based systems. ANT is shown to approximate an optimal Bayesian detector and an optimal minimum mean squared error (MMSE) estimator. We show that the theoretically optimum threshold and the optimal threshold obtained via Monte Carlo simulations agree to within 8%, with performance degradation of at most 2.1% for a variety of error probability mass functions. For a 2D-DCT implemented in a 45nm CMOS process, we find similar results where the thresholds have a 7.8% difference. Furthermore, both analysis and simulations indicate that ANT's probability of error detection is robust to the choice of the threshold.

In deep sub-micron processes, on-chip interconnect is becoming the delay bottleneck and predominant source of power consumption. Simultaneous switching of large buses pose a great challenge on peak current as well. In this paper, we present a novel bus coding technique, based on transition pattern codes (TPC), to perform joint optimization. A TPC scheme has been constructed employing a joint cost function on energy and peak current. The encoder and decoder of the code has been synthesized using a commercial 28nm process and the power, delay and area overhead has been evaluated. HSPICE simulations in 28nm show up to 70% reduction in peak current and 15% reduction in energy consumption compared to an uncoded bus.

Achieving robustness and energy efficiency in nanoscale CMOS process technologies is made challenging due to the presence of process, temperature, and voltage variations. Traditional fault-tolerance techniques such as N-modular redundancy (NMR) employ deterministic error detection and correction, e.g., majority voter, and tend to be power hungry. This paper proposes soft NMR that nontrivially extends NMR by consciously exploiting error statistics caused by nanoscale artifacts in order to design robust and energy-efficient systems. In contrast to conventional NMR, soft NMR employs Bayesian detection techniques in the voter. Soft voter algorithms are obtained through optimization of appropriate application aware cost functions. Analysis indicates that, on average, soft NMR outperforms conventional NMR. Furthermore, unlike NMR, in many cases, soft NMR is able to generate a correct output even when all N replicas are in error. This increase in robustness is then traded-off through voltage scaling to achieve energy efficiency. The design of a discrete cosine transform (DCT) image coder is employed to demonstrate the benefits of the proposed technique. Simulations in a commercial 45 nm, 1.2 V, CMOS process show that soft NMR provides up to 10× improvement in robustness, and 35 percent power savings over conventional NMR.

We have recently proposed the concept of soft N-modular redundancy (soft NMR) in order to design robust and energy-efficient computing systems in nanoscale processes, where soft NMR was shown to achieve orders-of-magnitude improvement in robustness with significant power savings over NMR. In this paper, we analyze the performance of soft NMR and compare it with that of NMR and algorithmic noise-tolerance (ANT). An 8-b multiplier and a DCT-based still image compression system in a commercial 45nm CMOS process is considered. Two metrics of system performance: system reliability Pe,sys, and signal-to-noise ratio (SN R) are analyzed. We show that soft NMR always outperforms NMR and that our analysis predicts Pe,sysand SNR to within 4.2% and 2.7dB on average, respectively, of the results of Monte Carlo simulations.