The directed self-assembly and multiple patterning (DSA-MP) lithography has shown its great potential in fabricating via/contact layers in sub-10-nm technology nodes. Existing studies have shown that using two different block copolymer (BCP) materials can reduce conflict numbers among guiding templates compared with those only using a single BCP material. However, given an arbitrary via/contact layout, there may still be many conflicts in an optimized template design and mask assignment solution. In this article, we explore the possibility of via manufacturability improvement with dummy via insertion for DSA-MP. We also propose a post-decomposition optimization flow composed of four heuristics to further resolve conflicts. The experimental results show that our flow can efficiently and effectively reduce conflicts by inserting dummy vias.

In sub 10-nm technology nodes, the directed self-assembly technology with multiple patterning lithography (DSA-MP) is a promising solution for contact/via layer fabrication. However, previous studies using multiple patterning with a single block copolymer (BCP) material still suffer from low via manufacturability due to limited types of feasible guiding templates. To mitigate the problem, multiple patterning in combination with two different BCP materials has been proposed, which contributes to more flexible DSA-compatible pattern matching. In this paper, we propose the first work of simultaneous guiding template assignment and layout decomposition with multiple BCP materials for general via layouts in DSA-MP. An optimal integer linear programming (ILP) formulation and a practical and sophisticated heuristic algorithm are proposed. Experimental results indicate that adopting two different BCP materials can greatly reduce conflict numbers compared with existing works using a single BCP material, and the proposed heuristic method can efficiently obtain good solutions.

Because of the delay of the next-generation lithography technologies, self-aligned double patterning (SADP) has become one of the major lithography solutions for sub-20-nm technology nodes. For advanced sub-10-nm nodes, self-aligned quadruple patterning (SAQP) or even self-aligned octuple patterning will be required. Due to considerable design complexity and unmanageable process variation, 1-D grid-based layout structure will be adopted, which can be achieved with sophisticated self-aligned multiple patterning (SAMP) process with the use of a cut mask. However, cut masks for arbitrary layouts are hardly manufacturable, because cut mask rules are limited by conventional 193-nm lithography. To the best of our knowledge, most of the existing SADP- and SAQP-aware detailed routers would fail to generate cut mask-friendly routing results for general SAMP. In this paper, we propose the first work of cut mask optimization with wire planning in SAMP full-chip routing. We first identify cut mask-aware routing rules to guide our router. Then, cut mask-aware wire planning, detailed routing, and postlayout modification techniques are proposed in the routing flow. Experimental results show that the proposed routing algorithms are effective in generating routing results with optimized cut masks.