In the context of the globalization of the Integrated Circuit (IC) industry, the Intellectual Property Cores (IPs) assume a pivotal role, offering the potential to streamline the development process and reduce costs. However, the use of IPs from third parties introduces the potential for malicious modifications, such as the insertion of hardware Trojans (HTs), which can compromise the security and reliability of hardware designs. Despite the advent of deep learning-based HT detection methods that leverage circuit sequences and graph data, which have overcome the limitations of a lack of a golden model and scalability issues, there are still shortcomings in the utilization of global and local features. We develop an HT detection method SFCM-HT based on a combination model of the graph convolutional network (GCN) and the gated recurrent unit (GRU). We transform the Register Transfer Level (RTL) design to a graph structure and model the graph as fixed-length sequences and innovatively construct the combination model to predict sequences related to HTs. We exploit the capacity of GCN to learn features locally and utilize circuit structure information globally, as well as the aptitude of GRU for learning and predicting circuit sequence features. We evaluate the model based on benchmark circuits in Trusthub. SFCM-HT detects Trojan sequences with 98.20% Precision and 98.76% Recall and effectively reduces detection time.

The globalization of the IC industry has led to hardware designers commonly adopting Third-Party Intellectual Property cores (3PIPs) to reduce design costs and time. However, over-reliance on untrustworthy 3PIPs may compromise the autonomy of ICs and provide opportunities for the Hardware Trojans (HT) implantation, thus reducing the security and trustworthiness of hardware designs. Existing methods of artificial intelligence have drawbacks of dependence on a golden HT-free model, low accuracy, and long detection time when identifying and detecting HTs in large-scale gate-level netlists (GLNs). To enhance the accuracy of HT detection in IP cores and reduce detection time, we propose a novel HT detection method using the controllability metric and the Gated Recurrent Unit (GRU) neural network to extract circuit sequence features and detect HTs. With the advantages of narrowing down the circuit detection range by the controllability metric and the simplicity and efficiency of the GRU neural network, our method achieves an average TPR detection accuracy of 95.5% and an average TNR detection accuracy of 99.6%. Compared with other existing methods, our method has high detection accuracy and effectively reduces the detection time.

The presence of always-on hardware Trojans (HTs) capable of continuously leaking sensitive information poses a significant threat to security, particularly in circuits designed for sensitive information protection. These HTs are engineered to operate stealthily, making their detection a formidable challenge. While existing hardware Trojan detection methodologies often rely on the identification of rare triggering characteristics, they prove inadequate for effectively identifying always-on HTs. This paper presents a novel approach to detect such HTs, which persistently leak critical information within circuits designed for sensitive information protection. By analyzing the characteristics of always-on information-leakage HTs, we propose CA4TJ, a corresponding quantifying metric to evaluate the correlation between sensitive information and the leaked port within gate-level netlists. Distinguished from conventional methods, the proposed approach eliminates the need for a reference model, thereby enhancing its practicality in real-world applications. The efficacy of this method is validated through extensive evaluations conducted on benchmark circuits, including those with intricate designs comprising up to one hundred thousand gates.

With the rapid development of AI hardware accelerators, applying deep learning-based algorithms to solve various low-level vision tasks on mobile devices has gradually become possible. However, two main problems still need to be solved: task-specific algorithms make it difficult to integrate them into a single neural network architecture, and large amounts of parameters make it difficult to achieve real-time inference. To tackle these problems, we propose a novel network, SYENet, with only 6K parameters, to handle multiple low-level vision tasks on mobile devices in a real-time manner. The SYENet consists of two asymmetrical branches with simple building blocks. To effectively connect the results by asymmetrical branches, a Quadratic Connection Unit(QCU) is proposed. Furthermore, to improve performance, a new Outlier-Aware Loss is proposed to process the image. The proposed method proves its superior performance with the best PSNR as compared with other networks in real-time applications such as Image Signal Processing(ISP), Low-Light Enhancement(LLE), and Super-Resolution(SR) with 2K60FPS throughput on Qualcomm 8 Gen 1 mobile SoC(System-on-Chip). Particularly, for ISP task, SYENet got the highest score in MAI 2022 Learned Smartphone ISP challenge.

Hardware Trojan is increasingly becoming a major threat in the filed of hardware security. To solve that security threat, we propose a novel strategy for hardware Trojan detection combining trustworthy design with thermal radiation analysis. We use ring oscillators to fill the vulnerable area of target IC, and their layouts can serve as the trustworthy reference. Ring oscillator's thermal radiation is related to its stage, so that the location and stage of ring oscillators can be extracted from thermal maps by k-means clustering. Removing, breaking or degrading ring oscillators to insert a hardware Trojan can be detected by thermal radiation analysis. Therefore, our countermeasure can efficiently and conveniently detect the insertion of hardware Trojan without fabricated golden-chip. Experimental results on FPGA show that our countermeasure can accurately identify the thermal radiation change of ring oscillators and be used for hardware Trojan detection.

Hardware trojan (HT) is increasingly becoming a major threat in the integrated circuit (IC) industry. Among all the countermeasures, academia is currently paying their most attention to the side-channel ones. However, most of the existing side-channel countermeasures need fabricated golden chips that are difficult to obtain practically. In this article, we propose a novel strategy for HT detection using the target chip's quiescent thermal maps and its active area (AA) shape from the GDS II file. The AA shape cannot expose the design information of the target chip and serves as the golden reference, which means that our countermeasure does not need fabricated golden chips anymore. In addition, this countermeasure cannot be influenced by process variation (PV) from the perspective of our detection mechanism. The results of the experiment on our designed YinHeFeiTeng-digital signal processor (YHFT-DSP) indicate that our countermeasure can effectively detect trojans with a very small scale.

Hardware Trojan (HT) is increasingly becoming a serious problem in the information security field. Compared to other countermeasures, thermal maps based detection can mitigate process variation (PV) and have a higher accuracy. However, HT cannot be differentiated from the others directly from the original thermal maps. Therefore, in this study, the authors first propose a general HT detection framework based on difference temperature matrix, and introduce the PV mitigation mechanism. Then, they demonstrate how principal component analysis can implement spatial projection transformation and expose HT signal. Finally, they introduce their experimental setup and design, and then validate their countermeasure with Xilinx field programmable gate arrays which are configured with the pure AES circuit and the infected AES circuits. The power proportions (PPs) of HTs in the different infected AES circuits are various. The experimental results indicate that their proposed countermeasure can clearly detect HT with 0.14% small PP.

As present, Differential Power Analysis (DPA) attack sample the power consumption information of chips using an oscilloscope which sample frequency is much larger than system global clock speed. Through the simulation of the S-box circuit in Advanced Encryption Standard (AES) and differential analysis of power consumption data, we find that, when reached an amount, the sample frequency's increasing has slight influence on the DPA. Yet when the sample frequency decreases, the cost data collected by the collection points tends to be random, which results in the correlation between the measurements of the power and the data being processed is not well revealed. Under the precondition of not impacting the effect of DPA, proper reduction in the sample frequency will not only compress the data but also increase the number of power trace. Thus the effect of the DPA is strengthened. Meanwhile, the cost of design the sampling system is reduced, which leaves more space for the improvement of the accuracy of the sampling system.

With the number of processor cores increasing in chip multi-processors (CMPs) and global wire delays increasing, networks on chip have been gaining wide acceptance for on-chip inter-core communication. This paper introduces a low latency Dynamic Virtual Output Queues Router (DVOQR), which can reduce the router latency to two cycles by leveraging look-ahead routing computation and virtual output address queues scheme. Simulation results show that network throughput on a 4×4 mesh increases by up to 46.9% and 28.6%, compared to wormhole router and virtual channel router, and that DVOQR outperforms doubled buffer virtual channel router by 1.9% under same input speedup. Network zero-load-latency also decreases by 25.6% and 41% respectively under random traffic. The results with place and route used by Cadence Encounter in TSMC 65nm technology display that the frequency of DVOQR can reach 1.4 GHz, the cell area of the router is only 0.424mm2and the power consumption is 274 mw under the 50% injection rate.