This paper presents a 16-bit, energy-efficient, fully dynamic successive-approximation-register (SAR) capacitance-to-digital converter (CDC) for single-ended capacitive sensors. A system-level correlated-double-sampling (CDS) scheme is proposed to suppress errors arising from comparator offset, low-frequency noise, and external interference. The delay time characteristics of the inverter-based amplifier (FIA) comparator are characterized for the first time, and an optimal delay time is determined through simulation. An LSB-repetition scheme improves low-noise performance. Dual digital-supply technique reduces the power consumption of the digital circuitry and also extend the delay time of digital delay elements with minimal power overhead, thereby improving energy efficiency. Fabricated in a 180-nm CMOS process, the CDC is validated using a capacitive MEMS pressure sensor, achieving a best resolution of 0.27 fF and a signal-to-noise ratio (SNR) of 82.6 dB among SAR CDCs. Consuming$2.85~\mu $W with a$56~\mu $s conversion time, it achieves a Walden figure-of-merit ($FoM_{w}$) of 15 fJ/step. The CDC attains a DNL of -0.76/+0.85 LSB and an INL of -9.16/+9.15 LSB without calibration. Experimental results demonstrate more than$16\times $improvement in interference rejection at 100 Hz and more than$7\times $improvement under 1000 Hz, compared to a non-CDS implementation.

This article presents a four-channel interface application-specific integrated circuit (ASIC) for infrared focal plane arrays (IRFPAs), where each channel integrates a programmable gain amplifier (PGA) with wide-range input common-mode adjustment capability and a 16-bit hybrid analog-to-digital converter (ADC) with resistor-sharing technique (RST). The flash stage of the ADC performs 5-bit most significant bits (MSBs) conversion, whose results are transferred to thermometer-coded capacitor array in the successive approximation register (SAR) stage, ensuring high linearity while maintaining conversion speed. This hybrid architecture of the ADC uses the RST by sharing the resistor ladder between the flash and SAR stages, reducing power consumption. The interface ASIC fabricated in the 180-nm CMOS technology achieves an input common-mode adjustment range of 0.169–3.269V. Operating at 2 MS/s with a 3.3-V supply, it achieves an 88.1-dB signal-to-noise-and-distortion ratio (SNDR) and consumes 13.97 mW/channel. The Schreier figure-of-merit (FoM) of the ADC reaches 171.2 dB/channel. Measured differential and integral nonlinearity (DNL/INL) are −0.38/+0.49 least significant bits (LSBs) and −2.2/+1.4 LSB, respectively.

This paper presents an event-driven readout integrated circuit (ROIC) for imaging and target-tracking infrared focal plane arrays (IRFPAs). The pixel circuit consists of event detection (ED) and imaging and trace detection (ITD). Based on the dynamic vision sensor (DVS) structure, ED encodes the temporal changes of infrared radiation into synchronized 1.5-bit events and transmits them to the off-chip postprocessor. When a moving target is recognized, the region of interest (ROI) window address will be feedback to ROIC and read out the image and trace information provided by ITD, which is based on infinite impulse response in the analog domain. These absolute intensities and multi-frame fused trace allow the post-processor to complete high-accuracy agile action recognition. This ROIC provides a spatiotemporal redundant compression and energy-efficient solution for fast-moving object detection and analysis. A prototype based on a 16×16 array of 20 µm pixel-pitch has been fabricated using a 0.18 µm 1P5M CMOS process, consuming [email protected] event and image frame frequency. Detailed test and measurement results of the prototype are presented.

This paper presents a low-power and energy-efficient capacitance-to-digital converter (CDC) for a single-end sensor based on correlated double sampling (CDS) technology. The CDS is accomplished by two opposite conversions, which reuse the comparator, CSENS, and CDAC. The proposed CDC eliminates the parasitic-dependent error caused by the comparator’s offset without extra consumption through the CDS. The simulation results show that the CDC can eliminate low-frequency interference and achieve anti-common-mode interference capabilities similar to differential circuits. To achieve low noise and high energy efficiency, the CDC employs a floating inverter amplifier (FIA) as the pre-amplifier of the comparator. Implemented in a 0.18 μm CMOS process, it consumes 0.91 μW from a 1.2 V supply. The simulation results show an effective number of 11.69 bits and an energy efficiency of 27.5 fJ per conversion step.