Spin-orbit torque magnetic tunnel junction (SOT-MTJ) devices have gained significant attention for energy-efficient computing, particularly in Logic-in-Memory (LiM) architectures. However, conventional SOT-MTJ-based write circuits suffer from excessive power dissipation due to the reliance on externally generated Spin Hall Effect (SHE) pulses, necessitating complex synchronization and additional circuit overhead. This work introduces a novel self-SHE pulse generation technique that eliminates the need for an external SHE pulse, simplifying the circuit design and significantly reducing energy consumption. Furthermore, the proposed design leverages 2D material-based SOT-MTJs, which exhibit superior charge-to-spin conversion efficiency, thereby enhancing write performance. The proposed write circuit is integrated into a 1-bit Arithmetic Logic Unit (ALU), which is further extended to a 4-bit ALU to demonstrate scalability in LiM applications. Simulation results using 45nm CMOS technology and Verilog-A models for 2D SOT-MTJs indicate that the proposed write circuit achieves a 16.049% improvement in area efficiency and a 20.72% reduction in energy consumption compared to conventional SHE-assisted SOT-MTJ write circuits. Additionally, the full adder incorporating the proposed write circuit demonstrates a 25.2% improvement in energy efficiency over existing designs. Monte Carlo simulations validate the robustness of the proposed approach under variations in oxide layer and free layer thickness. By eliminating external SHE pulse requirements and utilizing 2D SOT-MTJ technology, this work presents a significant advancement towards low-power, high-speed, and scalable spintronic computing architectures, making it a strong candidate for next-generation LiM-based processors.

This work presents a junction-engineered Schottky Ring Engineered Reconfigurable Nanowire Transistor (SR2NT) with a dual gate for the first time. Schottky Ring (SR) is present on either end of the Silicon Nanowires, resulting in an improved current for the device. This is because of an increase in the cross-section area for tunneling. The proposed device exhibits a very high ION/IOFFratio ~ 1010(ION ~ 10-6and IOFF ~ 10-16A) with relatively small threshold voltages (VTH) of 0.72 (-0.75) volts as compared to previously reported experimental data of 107and 2 (1.8) volts for n (p-FET) device respectively. This is owing to the presence of high-κ material as gate dielectric; hence, there will be an increase in the barrier tunneling. A Maximum Current Density of 1618 (884) kA cm-2 for n-FET (p-FET) is also reported at 50% scaled supply voltage. An improvement in the Subthreshold Slope (SS) of 56% (53%) and 51% (30%) is obtained as compared to the experimental dual gate and triple gate Nanowire transistors, respectively. The benchmarking results confirm that the SR2NT is a strong contender for future Nanoscale devices.

The impact of source/drain extension length (LEXT) and vertical sheet stacking on the transient response of the inverter, made up of nanosheet FETs, has been investigated. This study mainly focuses on overshoot/undershoot in the transient behavior of the inverter in continuation with its impact on propagation delay. It has been observed that propagation delay reduces with a symmetric increment of S/D LEXT. However, 4 ~ 5 nm of LEXT would be the optimum choice for source/drain extension length considering overshoot/undershoot. Away from this range of LEXT, a continued increment in overshoot/undershoot is observed owing to the increment/decrease in gate-to-drain resistance/capacitance, respectively. Furthermore, circuit level analysis done on the desire for high-drive capability through vertical sheet stacking shows that increasing sheet stacks decreases the propagation delay, as well as it also increases the overshoot/undershoots, which may damage the in-path level sensitive devices on an increased voltage level at the output of the inverter.