Due to the steady shrinking of technology node sizes, Self-Heating Effect (SHE) has become at the forefront of reliability and longevity concerns. Without careful consideration of the increased temperatures, reliability effects such as aging will be underestimated, putting the transistor and circuit at risk. SHE challenges and concerns are all amplified at cryogenic temperatures, as at low temperatures, multiple physical changes take effect, like the significant decrease of thermal conductivity, carriers’ mobility increase, and lower heat dissipation due to the low ambient temperature. The study of SHE at cryogenic temperatures is especially important in applications like quantum computing and space electronics. To accurately anticipate the SHE on the transistor, physics-based transistor and semiconductor simulation tools, Technology CAD (TCAD), are used. TCAD tools offer accurate, physics-based transistor SHE results, which designers can use to make informed decisions. However, TCAD tools can only deliver accurate SHE results after a manual, time-intensive calibration process. This calibration can only be done for operating temperatures and transistor configurations with existing experimental data. The reliance on experimental data for calibration and the constant need for recalibration restrict the scope of the design process to only a limited subset of configurations. In this work, we propose the first data-driven surrogate Convolutional Neural Network (CNN)-based TCAD thermal model for SHE thermal profile and channel hotspot prediction. Our approach enables designers to sweep a huge amount of different operating temperatures without the dependency on available experimental data or the constant need for model recalibration, while achieving a thermal profile prediction accuracy of 99.91%, a thermal profile extrapolation accuracy of 96.88%, hotspot prediction average error of 0.127%, and hotspot extrapolation average error of 1.65%. All results are compared to calibrated TCAD thermal model simulation results. Our model also alleviates the high computational cost and low throughput associated with TCAD tools by offering a time speedup of more than 13 000 x for both prediction and extrapolation tasks.

Reliability is one of the key concerns in circuit design. The circuit must be able to tolerate transistor degradation to sustain reliability against timing failure. Whether a transistor is degraded due to noise, aging, or poor manufacturing, a circuit must uphold a timing error-free functionality over its entire projected lifetime. Transistors are hardened (designed stronger than necessary) to tolerate these degradations. However, hardening (e.g., widening the transistors) comes at the cost of additional area and power. Hence, it is necessary to identify and selectively harden specific transistors within a circuit. In this work, transistors that prolong a circuit’s delay when they are degraded are termed “susceptible”, and thus, are to be hardened. Identifying the susceptible transistors within a circuit is a complex task, for example, Monte Carlo circuit simulations require days to identify susceptible transistors in a single circuit. Consequently, current solutions are costly in terms of time and limited in their application. Instead, machine learning (ML) can offer a fast (inference in seconds) and universal (applicable to unseen circuits) alternative. However, traditional ML techniques struggle with inference on topology-based problems, while recent graph neural networks (GNNs) excel in these applications. Therefore, this work presents the first ML to classify susceptible transistors with GNNs. We use GNNs, specifically Graph Attention Networks (GAT), because the topology of the cell strongly affects how each transistor degradation affects performance. For instance, series-connected transistors amplify their impact, while parallel-connected ones can offset each other’s influence. Our GAT-based approach employs a heterogeneous graph in combination with GAT’s attention mechanism to capture the circuit’s topology and its impact on the analysis. Our evaluation demonstrates the capability of our approach to classifying transistors according to their impact within the ASAP7 standard cell library’s standard cells in mere 0.04 s (compared to days of Monte Carlo simulation time) while achieving 80.4% accuracy on unseen circuits.