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Nicholas Parnenzini

dblp:382/3683 · DBLP profile ↗
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1ranked-venue papers
0as first author
1since 2021 · last 2025
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
GPUs and heterogeneous computing · 50% Parallel and multicore computing · 25% Processor architecture and microarchitecture · 25%
Theoretical computer science
1 paper
Graph algorithms and graph theory · 100%

Topics — the 4 heaviest of 5, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Processor architecture and microarchitecture › microprocessor design › processor core design
functional units
0.912025
SparseWeaver: Converting Sparse Operations as Dense Operations on GPUs for Graph Workloads · HPCA 2025
GPUs and heterogeneous computing
GPU graph processing
0.912025
SparseWeaver: Converting Sparse Operations as Dense Operations on GPUs for Graph Workloads · HPCA 2025
GPUs and heterogeneous computing
GPU microarchitecture
0.912025
SparseWeaver: Converting Sparse Operations as Dense Operations on GPUs for Graph Workloads · HPCA 2025
Parallel and multicore computing
load balancing
0.912025
SparseWeaver: Converting Sparse Operations as Dense Operations on GPUs for Graph Workloads · HPCA 2025

Methods — techniques the papers use, named apart from their topics

hardware-software co-design · 1.7
YearPublicationVenuePosition
2025 SparseWeaver: Converting Sparse Operations as Dense Operations on GPUs for Graph Workloads
abstract
Thanks to their scalable parallel processing capability, GPUs are promising computing resources for graph processing, in which identical operations are applied to a large number of edges and vertices. However, the sparsity and skewness of real-world graphs cause imbalanced workloads across GPU threads within the same warp, thus impeding efficient processing on the GPU. To mitigate this workload imbalance problem, existing works propose workload balancing hardware and software schemes. However, these solutions often suffer from additional memory overhead or increased computations and communication overheads during inter-warp and intra-warp synchronization. This work proposes a new hardware-software collaborative graph processing framework, SparseWeaver, that converts sparse operations in graph processing into dense operations using graph topology and makes the workloads balanced across GPU threads. Based on the analysis of common patterns in software schemes, we propose Weaver, a new lightweight GPU functional unit microarchitecture that fully leverages the benefits of the GPU architecture and exploits memory access locality. We prototype SparseWeaver on the open-source RISC-V Vortex GPU and demonstrate 2.36 times faster execution time compared to state-of-the-art schemes while incurring a low area overhead of 0.045% from increased dedicated logic registers.
Shinnung Jeong, Liam Cooper, Ju Min Lee, Heelim Choi, Nicholas Parnenzini, Chihyo Ahn, Yongwoo Lee 0001, Hanjun Kim 0001, Hyesoon Kim
HPCA5