CPU-FPGA SoC architectures with multiple shared coherent caches reduce inter-component communication overhead and enable efficient CPU-FPGA collaboration through task partitioning. However, existing studies primarily focus on optimizing partitioning units and ignore the benefits and diversity of coherent cache architectures on CPU-FPGA SoCs, leading to extra communication overhead in the final partitioning decisions. To address this, we propose TAPCA, a memory interface-aware task partitioning framework that integrates coherent cache management and selection. TAPCA includes an adaptive partitioning unit generator to identify essential application structures for efficient design space exploration, a design space exploration module to profile partitioning units across various design points, a memory management modeling module based on cache bypassing to match each unit with its optimal memory architecture and assess communication overhead, and a knapsack problem partitioning solver to determine partitioning decisions with appropriate configurations of hardware and memory architectures for partitioning units.

The traditional shared memory architectures (MAs) used for CPU-FPGA interaction on FPGA system-on-chip (FPSoC) platforms lack the support for field-programmable gate array (FPGA) caches, resulting in increased FPGA access time to shared system data and CPU-FPGA interference. The full coherency architecture (FCA) enables the implementation of FPGA caches to mitigate these challenges. This brief unveils features of FCA including the basic performance and its influence on CPU-FPGA interference of FPSoCs, revealing that FCA has an up to 70% bandwidth improvement when FPGA cache hits, a 49% bandwidth degradation when FPGA cache misses and 27.9% and 22% improvement on CPU-FPGA interference when CPU accessing CPU caches and DDR, respectively. An automated memory management framework is accordingly proposed to select the optimal MAs based on the analysis of cache hit ratio and execution information, and case studies prove the effectiveness of the framework.