The Cell-Aware (CA) methodology has become essential to detect and diagnose manufacturing intra-cell defects in modern semiconductor technologies. It characterizes standard cells by creating a defect-detection matrix, which serves as a reference that maps stimuli to the specific defects they can detect. Its limitation is that CA approach needs a number of time-consuming analog simulations to create the matrix. In [1] a graph-based methodology able to reduce the number of simulations to perform, called Transistor Undetectable Defect eLiminator (TrUnDeL), was presented. TrUnDeL can identify undetectable stimulus/defect pairs that are then excluded from the analog simulations. However, its use is limited to combinational cells and does not offer any guidance on handling sequential cells, which are usually the most complex cells. In this paper we present a new version of TrUnDeL that supports sequential cells analysis. Experiments conducted on sequential cells from two standard cell industrial libraries demonstrate that the CA generation time is reduced by 30% without compromising accuracy.

Testing advanced memories is essential for ensuring modern System-on-Chip quality. As transistor size continues to shrink, the probability of the occurrence of manufacturing defects increases, making conventional functional testing of SRAMs inadequate for achieving required Defect Parts per Million (DPPM). To address this issue, a novel structural testing approach using the Cell-Aware (CA) test methodology has been proposed in [1]. With this methodology, structural test patterns are obtained through an Automatic Test Pattern Generator (ATPG) by exploiting analog CA models (i.e., based on exhaustive analog simulations) for SRAM primary blocks. However, the generation of CA models through analog simulations is time-consuming and technology dependent. A methodology, namely TrUnDeL proposed in [2], is used to accelerate the CA model generation, combining a switch-level graph-based solution and analog simulations. In this work, we propose an adaptation of TrUnDeL to generate the CA models, using only the switch-level graph-based simulations. TrUnDeL CA models are then used by the ATPG to generate structural test patterns. Through a validation flow, we demonstrate that the aforementioned patterns, generated without running any analog simulations, achieve nearly the same fault coverage as the test patterns generated using exhaustive analog simulations on an SRAM case study. The time required to generate CA models is drastically reduced with TrUnDeL, from 1 hour to 15 seconds for the considered case study.

The reduction in transistor size in modern Integrated Circuits (ICs) has led to an increase in manufacturing defects within standard cells, also known as intra-cell defects. Detecting these defects and localizing them through diagnosis is crucial for achieving a fast yield ramp-up and ensuring a low test escape rate. Traditional fault models, such as stuckat and transition, do not effectively represent intra-cell defects. To address this issue, the Cell-Aware (CA) methodology was introduced. However, this technique involves time-consuming analog SPICE simulations to characterize standard cells. This paper presents a methodology, called Transistor Undetectable Defect eLiminator (TrUnDeL), based on graph theory to speed up the CA model generation process. Our methodology identifies undetectable defects for each stimulus applied at the inputs of the cell, which are then excluded from the analog simulations. We applied TrUnDeL to two libraries from STMicroelectronics (P28 and C28) to identify the undetectable stimulus/defect pairs, so that analog simulations are performed only on the remaining pairs. As a result, the CA model generation process time is reduced by a factor of 3. Finally, we applied TrUnDeL to a SRAM bitcell case study and demonstrated that the obtained results are consistent with its existing CA model.

As modern Integrated Circuits (ICs) feature ever-smaller transistors, the prevalence of manufacturing defects within standard cells (intra-cell defects) has increased. Detecting and localizing these defects is crucial to guarantee a fast yield ramp-up and to maintain a low-test escape rate. Unfortunately, traditional fault models such as stuck-at and transition fail to adequately represent intra-cell defects. Cell-Aware (CA) was introduced to tackle this problem, but it requires time-consuming analog SPICE simulations for standard cell characterization. To speed-up the CA model generation process, this paper presents a methodology based on graph theory called Transistor Undetectable Defect Eliminator (TrUnDeL). This methodology identifies undetectable defects for each stimulus applied to the inputs of the cell, subsequently excluding them from the analog simulations to perform. TrUnDeL uses rule-based and propagation-based techniques and was trialed on combinational and sequential cells of two 28nm libraries from STMicroelectronics (P28 and C28) to identify the undetectable stimulus/defect pairs, so that analog simulations are performed only on the remaining pairs. As a result, the CA model generation process time was reduced by a factor of 3 compared to a standard SPICE-based generation process.