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Rana Altay

dblp:383/1829 · DBLP profile ↗
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2ranked-venue papers
0as first author
2since 2021 · last 2024
0000-0002-1813-5048ORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2 · 2 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
Electronic design automation · 100%

Topics — the 5 heaviest of 5, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation › hardware verification and test › design for testability
built-in self-test
0.812024
Late Breaking Results: Efficient Built-in Self-Test for Microfluidic Large-Scale Integration (mLSI) · DAC 2024
Electronic design automation
hardware verification and test
0.812024
Late Breaking Results: Efficient Built-in Self-Test for Microfluidic Large-Scale Integration (mLSI) · DAC 2024
Electronic design automation
microfluidic biochip design
0.812024
LaMUX: Optimized Logic-Gate-Enabled High-Performance Microfluidic Multiplexer Design · DAC 2024
Electronic design automation › hardware verification and test
test data volume reduction
0.812024
Late Breaking Results: Efficient Built-in Self-Test for Microfluidic Large-Scale Integration (mLSI) · DAC 2024
Electronic design automation
logic synthesis
0.212024
LaMUX: Optimized Logic-Gate-Enabled High-Performance Microfluidic Multiplexer Design · DAC 2024

Methods — techniques the papers use, named apart from their topics

mixed coding strategy · 0.8graph coloring · 0.8gate structure design · 0.8built-in self-test · 0.8
YearPublicationVenuePosition
2024 Late Breaking Results: Efficient Built-in Self-Test for Microfluidic Large-Scale Integration (mLSI)
abstract
Control channels on microfluidic large-scale integration (mLSI) chips are prone to blockage and leakage defects. In this work, we propose a built-in self-test (BIST) method that drastically improves the test efficiency. Given n to-be-tested control channels, we reduced the number of test patterns for blockage and leakage tests from [EQUATION] to 1, and from ⌈log2(n + 1)⌉ to ⌈log2(χ(G) + 1)⌉, respectively, where χ(G) denotes the vertex chromatic number of a graph G consisting of n vertices. We fabricated our design and demonstrated the feasibility and efficiency of our method.
Mengchu Li, Hanchen Gu, Yushen Zhang, Siyuan Liang 0002, Hudson Gasvoda, Rana Altay, Ismail Emre Araci, Tsun-Ming Tseng, Tsung-Yi Ho, Ulf Schlichtmann
DAC6
2024 LaMUX: Optimized Logic-Gate-Enabled High-Performance Microfluidic Multiplexer Design
abstract
After decades of development, flow-based microfluidic biochips have become an increasingly attractive platform for biochemical experiments. The fluid transportation and the on-chip device operation are controlled by microvalves, which are driven by external pneumatic controllers. To meet the increasingly complex experimental demands, the number of microvalves has significantly increased, making it necessary to adopt multiplexers (MUXes) for the actuation of microvalves. However, existing MUX designs have limited coding capacities, resulting in area overhead and excessive chip-to-world interface. This paper proposes a novel gate structure for modifying the current MUX architecture, along with a mixed coding strategy that achieves the maximum coding capacity within the modified MUX architecture. Additionally, an efficient synthesis tool for the mixed-coding-based MUXes (LaMUXes) is presented. Experimental results demonstrate that the LaMUX is exceptionally efficient, substantially reducing the usage of pneumatic controllers and microvalves compared to existing MUX designs.
Siyuan Liang 0002, Yushen Zhang, Rana Altay, Hudson Gasvoda, Mengchu Li, Ismail Emre Araci, Tsun-Ming Tseng, Ulf Schlichtmann, Tsung-Yi Ho
DAC3