As AI models outpace the capabilities of single processors, interconnects across chips have become a critical enabler for scalable computing. These processors exchange massive amounts of data at cache-line granularity, prompting the adoption of new interconnect protocols like CXL, NVLink, and UALink, designed for high bandwidth and small payloads. However, the increasing transfer rates of these protocols heighten susceptibility to errors. While mechanisms like Cyclic Redundancy Check (CRC) and Forward Error Correction (FEC) are standard for reliable data transmission, scaling chip interconnects to multi-node configurations introduces new challenges, particularly in managing silently dropped flits in switching devices.

DRAM technology has continually evolved to meet escalating demands for higher memory capacity and greater data bandwidth. This progression, however, has also led to increases in both storage and transfer errors, primarily due to the smaller transistors and higher transfer rates. To combat these errors, systems employ both Error Correcting Codes (ECC) and Cyclic Redundancy Check (CRC), despite their substantial performance and energy costs. This paper introduces a novel ECC, Dual-Axis ECC (DA-ECC), which provides unified protection against both storage and transfer errors. DA-ECC enhances traditional ECC approaches to correct one half-chipkill error, two DQ errors, or one transfer error on the Data Strobe (DQS) signal in × 8 DRAM chips. This comprehensive protection eliminates the need for additional CRC mechanisms. Our evaluations demonstrate that DA-ECC not only enhances system performance by up to 1.6% but also improves DRAM energy efficiency by up to 8.2% while providing a robust solution to the dual challenges of storage and transfer errors.

Contemporary data center CPUs are experiencing an unprecedented surge in core count. This trend necessitates scrutinized Last-Level Cache (LLC) strategies to accommodate increasing capacity demands. While DRAM offers significant capacity, using it as a cache poses challenges related to latency and energy. This paper introduces Native DRAM Cache (NDC), a novel DRAM architecture specifically designed to operate as a cache. NDC features innovative approaches, such as conducting tag matching and way selection within a DRAM subarray and repurposing existing precharge transistors for tag matching. These innovations facilitate Caching-In-Memory (CIM) and enable NDC to serve as a high-capacity LLC with high set-associativity, low-latency, high-throughput, and low-energy. Our evaluation demonstrates that NDC significantly outperforms state-of-the-art DRAM cache solutions, enhancing performance by $\mathbf{2.8 \%} / \mathbf{52.5 \%} / \mathbf{44.2 \%}$ (up to $8.4 \% / 140.6 \% / 85.5 \%$) in SPEC/NPB/GAP benchmark suites, respectively.