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Jorge Cabrera 0003

dblp:383/4092 · DBLP profile ↗
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1ranked-venue papers
0as first author
1since 2021 · last 2024
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 since 2021Software engineering, systems software and programming languages · 1 · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Hardware accelerators and domain-specific architectures · 70% Cloud and datacenter computing · 23% Integrated circuit design · 7%

Topics — the 5 heaviest of 6, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Hardware accelerators and domain-specific architectures › accelerator architecture
datacenter accelerator
0.812024
Intel Accelerators Ecosystem: An SoC-Oriented Perspective : Industry Product · ISCA 2024
Cloud and datacenter computing › datacenter architecture
datacenter tax offload
0.812024
Intel Accelerators Ecosystem: An SoC-Oriented Perspective : Industry Product · ISCA 2024
Hardware accelerators and domain-specific architectures › accelerator architecture
on-chip accelerator
0.812024
Intel Accelerators Ecosystem: An SoC-Oriented Perspective : Industry Product · ISCA 2024
Hardware accelerators and domain-specific architectures › accelerator integration
on-chip accelerator integration
0.812024
Intel Accelerators Ecosystem: An SoC-Oriented Perspective : Industry Product · ISCA 2024
Integrated circuit design
system-on-chip
0.212024
Intel Accelerators Ecosystem: An SoC-Oriented Perspective : Industry Product · ISCA 2024

Methods — techniques the papers use, named apart from their topics

virtualization · 0.8accelerator sharing · 0.8
YearPublicationVenuePosition
2024 Intel Accelerators Ecosystem: An SoC-Oriented Perspective : Industry Product
abstract
A growing demand for hyperscale services has compelled hyperscalers to deploy more compute resources at an unprecedented pace, further accelerated by the demise of Dennard scaling. Meanwhile, a considerable portion of the compute resources are consumed to execute common functions present across the hyperscale services, i.e., datacenter taxes. These challenges motivated many to explore specialized accelerators for these functions. Leading such a technology trend, Intel has integrated diverse on-chip accelerators into its recent flagship datacenter CPU products. Furthermore, to support the easy and efficient use of these accelerators for successful deployment in production hyperscale services, Intel has developed a hardware/software ecosystem. In this paper, we first focus on Intel’s holistic efforts to build the hardware/software ecosystem, presenting key SoC-level features that facilitate efficient CPU-accelerator interaction, effortless programming and use, and scalable accelerator sharing and virtualization. Next, we delve into the functions, microarchitectures, and software stacks of three new on-chip accelerators: Data Streaming Accelerator (DSA), In-memory Analytics Accelerator (IAA), and Dynamic Load Balancer (DLB). Lastly, we demonstrate that Intel’s on-chip accelerators can not only significantly reduce the datacenter taxes but also accelerate data-intensive applications essential for hyperscale services, with little effort to use the accelerators.
Ren Wang 0001, Narayan Ranganathan, Philip Lantz, Vivekananthan Sanjeepan, Jorge Cabrera 0003, Atul Kwatra, Rajesh Sankaran, Ipoom Jeong, Nam Sung Kim
ISCA8