Demo Data from EDBT 2026 / reviewers in the wild / expert
Yucan Wu
dblp:383/4227
· DBLP profile ↗
1ranked-venue papers
0as first author
1since 2021 · last 2024
0009-0002-7995-719XORCID · reported
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1 · 1 since 2021Software engineering, systems software and programming languages · 1 · 1 since 2021
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Processor architecture and microarchitecture · 56% GPUs and heterogeneous computing · 44% |
Topics — the 3 heaviest of 3, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
GPUs and heterogeneous computing
GPU architecture |
0.8 | 1 | 2024 | GhOST: a GPU Out-of-Order Scheduling Technique for Stall Reduction · ISCA 2024 |
Processor architecture and microarchitecture › out-of-order execution
out-of-order scheduling |
0.8 | 1 | 2024 | GhOST: a GPU Out-of-Order Scheduling Technique for Stall Reduction · ISCA 2024 |
Processor architecture and microarchitecture
out-of-order execution |
0.2 | 1 | 2024 | GhOST: a GPU Out-of-Order Scheduling Technique for Stall Reduction · ISCA 2024 |
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2024 | GhOST: a GPU Out-of-Order Scheduling Technique for Stall ReductionabstractGraphics Processing Units (GPUs) use massive multi-threading coupled with static scheduling to hide instruction latencies. Despite this, memory instructions pose a challenge as their latencies vary throughout the application’s execution, leading to stalls. Out-of-order (OoO) execution has been shown to effectively mitigate these types of stalls. However, prior OoO proposals involve costly techniques such as reordering loads and stores, register renaming, or two-phase execution, amplifying implementation overhead and consequently creating a substantial barrier to adoption in GPUs. This paper introduces GhOST, a minimal yet effective OoO technique for GPUs. Without expensive components, GhOST can manifest a substantial portion of the instruction reorderings found in an idealized OoO GPU. GhOST leverages the decode stage’s existing pool of decoded instructions and the existing issue stage’s information about instructions in the pipeline to select instructions for OoO execution with little additional hardware. A comprehensive evaluation of GhOST and the prior state-of-the-art OoO technique across a range of diverse GPU benchmarks yields two surprising insights: (1) Prior works utilized Nvidia’s intermediate representation PTX for evaluation; however, the optimized static instruction scheduling of the final binary form negates many purported improvements from OoO execution; and (2) The prior state-of-the-art OoO technique results in an average slowdown across this set of benchmarks. In contrast, GhOST achieves a $\mathbf{3 6 \%}$ maximum and $6.9 \%$ geometric mean speedup on GPU binaries with only a $0.007 \%$ area increase, surpassing previous techniques without slowing down any of the measured benchmarks. Ishita Chaturvedi, Bhargav Reddy Godala, Yucan Wu, Konstantinos Iliakis, Panagiotis-Eleftherios Eleftherakis, Sotirios Xydis, Dimitrios Soudris, Tyler Sorensen 0001, Simone Campanoni, Tor M. Aamodt, David I. August |
ISCA | 3 |