Demo Data from EDBT 2026 / reviewers in the wild / expert
Yongtong Wu
dblp:383/5704
· DBLP profile ↗
3ranked-venue papers
1as first author
3since 2021 · last 2026
0009-0006-0482-0382ORCID · corroborated
Domains — the database's venue-derived domains; a paper can count in several
Computer networks · 3 · 1 first-author · 3 since 2021
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Interconnection networks and networks-on-chip · 39% Cloud and datacenter computing · 30% Distributed systems · 30% | |
| Computer networks
1 paper |
Software-defined and programmable networks · 100% |
Topics — the 5 heaviest of 6, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Cloud and datacenter computing
datacenter network |
0.8 | 1 | 2024 | RB2: Narrow the Gap between RDMA Abstraction and Performance via a Middle Layer · INFOCOM 2024 |
Interconnection networks and networks-on-chip
remote direct memory access |
0.8 | 1 | 2024 | RB2: Narrow the Gap between RDMA Abstraction and Performance via a Middle Layer · INFOCOM 2024 |
Distributed systems
remote procedure call |
0.8 | 1 | 2024 | RB2: Narrow the Gap between RDMA Abstraction and Performance via a Middle Layer · INFOCOM 2024 |
Software-defined and programmable networks
network programming |
0.3 | 1 | 2025 | High-level Programming for Application Networks · NSDI 2025 |
Interconnection networks and networks-on-chip
interconnection networks |
0.2 | 1 | 2024 | RB2: Narrow the Gap between RDMA Abstraction and Performance via a Middle Layer · INFOCOM 2024 |
Methods — techniques the papers use, named apart from their topics
microbenchmarking · 0.8memory subsystem optimization · 0.8adaptive batching · 0.8
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2026 | DualPath: Accelerating Agentic LLM Inference by Harvesting Disaggregated KV-Cache Storage I/OabstractThe performance of multi-turn, agentic LLM inference is increasingly dominated by KV-Cache storage I/O rather than computation. In prevalent disaggregated architectures, loading the massive KV-Cache from external storage creates a fundamental imbalance: storage NICs on prefill engines become bandwidth-saturated, while those on decoding engines remain idle. This asymmetry severely constrains overall system throughput. Yongtong Wu, Shaoyuan Chen, Rilin Huang, Yixuan Tan, Yinmin Zhong, Xin Jin 0008, Panpan Huang |
SIGCOMM | 1 |
| 2025 | High-level Programming for Application Networks
Xiangfeng Zhu, Banruo Liu, Yongtong Wu, Nikola Bojanic, Jingrong Chen 0002, Gilbert Louis Bernstein, Arvind Krishnamurthy, Sam Kumar, Ratul Mahajan, Danyang Zhuo |
NSDI | 4 |
| 2024 | RB2: Narrow the Gap between RDMA Abstraction and Performance via a Middle LayerabstractAlthough the native RDMA interface allows for high throughput and low latency, its low-level abstraction raises significant programming challenges. Consequently, numerous systems encapsulate the RDMA interface into more user-friendly high-level abstractions such as Socket, MPI, and RPC. However, this ease of development often incurs considerable performance degradation. To address this trade-off, this paper introduces RB2, a high-performance RDMA-based Distributed Ring Buffer (DRB). RB2serves as a middle layer that effectively conceals the low-level details of the RDMA interface while also facilitating extension to other high-level abstractions.Nonetheless, it is non-trivial for DRBs to preserve the RDMA performance. We optimize the performance of RB2in three aspects. First, we perform micro-benchmarks to identify the pointer synchronization methods that are seemingly counter-intuitive but offer optimal performance improvements. Second, we propose an adaptive batching mechanism to alleviate the limitations of conventional fixed batching. Finally, we build an efficient memory subsystem using various optimization techniques. RB2outperforms SOTA designs by achieving 2.5 × to 7.5 × throughput while maintaining comparable tail latency for small messages. Haifeng Sun 0004, Yixuan Tan, Yongtong Wu, Qun Huang 0001, Xin Yao 0008, Gong Zhang 0001 |
INFOCOM | 3 |