Processing-in-Memory (PIM) architectures enable computation directly within DRAM and help combat the memory wall problem. While commodity DRAM has been demonstrated for data movement and bulk-bitwise PIM, data must be reorganized away from row-wise ordering and byte addressability used by typical processors into a column-ordering where bytes and words are spread across rows within a single column since there is no mechanism to move data between bitlines which is required for many computational operations including addition and multiplication. In this paper, we propose a DRAM subarray design that enables in-DRAM bit-shifting for open-bitline architectures. By adding migration cells at the top and bottom of each subarray, bidirectional bit-shifting may be conducted within any given row. In this paper we present initial findings and evaluation of potential timing and energy analysis using a combination of approaches from VLSI layout, spice simulation and demonstrate integration into NVMain-PIM a simulator extended with DRAM PIM primitives.

Computing-in-memory (CIM) has been demonstrated across various memory technologies, from memristive crossbars for analog dot-products to large-scale digital bitwise operations in commodity DRAM and other non-volatile memory technologies. However, current CIM solutions face challenges related to latency and reliability. CIM fidelity lags considerably behind standard memory access fidelity. Furthermore, bulkbitwise CIM, though highly parallel, requires long latency for multiplication and addition due to bit-serial execution. This paper presents Count2Multiply, a digital CIM framework that performs multiplication, addition, and other operations using high-radix, massively parallel counting enabled by bulk-bitwise inmemory operations. Designed to meet fault tolerance requirements, Count2Multiply integrates traditional row-wise error correction codes, such as Hamming and BCH, to address the high error rates in existing CIM designs. We demonstrate Count2Multiply in commodity DRAMs, achieving on average 1.5× speedup, 4.6× higher energy efficiency (GOPS/Watt), and 4.4× better area efficiency (GOPS/mm2) over NVIDIA A100; and 9.7×, 8.1×, and 12.9× improvements, respectively, over SIMDRAM.

The rapid advancement in genomic sequencing technologies has resulted in an explosion of data, creating substantial computational bottlenecks in DNA analysis workloads. Applications such as DNA classification are particularly impacted due to their reliance on intensive, large-scale pattern matching. Existing hardware accelerator and software solutions are increasingly unable to manage the scale and energy demands of these datasets, highlighting the need for architectures that can perform faster and more efficient pattern matching. To address these challenges, we propose NP-CAM: a data-optimized, CAMbased accelerator designed for parallel and energy-efficient DNA classification. NP-CAM harnesses a network-on-chip to implement a novel optimized indexing and CAM partitioning scheme that reduces the active search space, allowing significant scalability. We demonstrate results for NP-CAM on commodity 10T binary CAM cell designs. Our experimental evaluations show that NPCAM achieves a simultaneous$65 \times$improvement in sequence throughput and an over$173 \times$improvement in energy efficiency over state-of-the-art hardware solutions on existing small viral workloads. We go on to demonstrate feasibility for larger bacterial and fungal workloads, enabling scalable DNA classification in the era of large-scale genomic data.