EDBT 2026 Demo / reviewers in the wild / expert
Roger C. Su
dblp:383/7494
· DBLP profile ↗
2ranked-venue papers
1as first author
2since 2021 · last 2026
0000-0003-0176-3264ORCID · corroborated
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1 · 1 first-author · 1 since 2021Software engineering, systems software and programming languages · 1 · 1 since 2021Theory of computation · 1 · 1 since 2021
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Network and information security
1 paper |
Hardware security and side channels · 100% | |
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Processor architecture and microarchitecture · 100% | |
| Theoretical computer science
1 paper |
Automated reasoning and model checking · 100% |
Topics — the 3 heaviest of 4, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Hardware security and side channels
microarchitectural attacks |
0.9 | 1 | 2025 | Structural Operational Semantics for Functional and Security Verification of Pipelined Processors · CAV (1) 2025 |
Hardware security and side channels › microarchitectural attacks
transient execution attack |
0.9 | 1 | 2025 | Structural Operational Semantics for Functional and Security Verification of Pipelined Processors · CAV (1) 2025 |
Automated reasoning and model checking
model checking |
0.9 | 1 | 2025 | Structural Operational Semantics for Functional and Security Verification of Pipelined Processors · CAV (1) 2025 |
Methods — techniques the papers use, named apart from their topics
structural operational semantics · 2.6model checking · 2.6
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2026 | Weak Memory Model Formalisms: Introduction and SurveyabstractABSTRACT Memory models define the order in which accesses to shared memory in a concurrent system may be observed to occur. Such models are a necessity since program order is not a reliable indicator of execution order , due to microarchitectural features or compiler transformations. Concurrent programming, already a challenging task, is thus made even harder when weak memory effects must be addressed. A rigorous specification of weak memory models is therefore essential to make this problem tractable for developers of safety‐ and security‐critical, low‐level software. In this paper we survey the field of formalisations of weak memory models, including their specification, their effects on execution, and tools and inference systems for reasoning about code. To assist the discussion we also provide an introduction to two styles of formal representation found commonly in the literature (using a much simplified version of Intel's x86 as the example): a step‐by‐step construction of traces of the system ( operational semantics ); and with respect to relations between memory events ( axiomatic semantics ). The survey covers some long‐standing hardware features that lead to observable weak behaviours, a description of historical developments in practice and in theory, an overview of computability and complexity results, and outlines current and future directions in the field. Roger C. Su, Robert Colvin |
Concurr. Comput. Pract. Exp. | 1 |
| 2025 | Structural Operational Semantics for Functional and Security Verification of Pipelined ProcessorsabstractAbstract The design of computer microarchitectures is a challenging task, involving a trade-off between efficiency and security. In the literature, two concerns which are affected by the details of the microarchitecture – formal assembly semantics, and vulnerability discovery and mitigation – are often addressed separately. In this paper we provide a structural operational semantics for pipelined microprocessors (Arm, x86, RISC-V) that is based on a regular understanding of microarchitectural features (pipelines, branch prediction, caches, privilege checks), conforms to established memory consistency models, and exposes the Spectre and Meltdown vulnerabilities. A key point is that the operational rules correspond to stages of the pipeline and are based almost entirely on syntactic aspects of fetched instructions, as is generally understood to be the case in real pipelines. We develop a model checker based closely on the semantics, which we use to experimentally validate the model and to provide the basis for security analyses. Robert Colvin, Roger C. Su |
CAV (1) | 2 |