In low-light environments, event cameras suffer from sparse and noisy outputs. We propose ASTEF, a near-sensor FPGA architecture using adaptive temporal filtering and dynamic thresholding to improve signal quality under poor illu-mination. Implemented on the Zynq-7000 SoC, ASTEF reduces Slice LUTs by 83.91% and 93.49% compared to HMAX and HARP, respectively, while lowering dynamic power by up to 83.88%. A Python-based simulator further verifies its robustness, outperformina ROI-based models in dark scenes.

With the growing demand for enhanced performance and scalability in cloud applications and systems, data center architectures are evolving to incorporate heterogeneous computing fabrics that leverage CPUs, GPUs, and FPGAs. Unlike traditional processing platforms like CPUs and GPUs, FPGAs offer the unique ability for hardware reconfiguration at runtime, enabling improved and tailored performance, flexibility, and acceleration. FPGAs excel at executing large-scale search optimization, acceleration, and signal processing tasks while consuming low power and minimizing latency. Major public cloud providers, such as Amazon, Huawei, Microsoft, Alibaba, and others, have already begun integrating FPGA-based cloud acceleration services into their offerings. Although FPGAs in cloud applications facilitate customized hardware acceleration, they also introduce new security challenges that demand attention. Granting cloud users the capability to reconfigure hardware designs after deployment may create potential vulnerabilities for malicious users, thereby jeopardizing entire cloud platforms. In particular, multi-tenant FPGA services, where a single FPGA is divided spatially among multiple users, are highly vulnerable to such attacks. This article examines the security concerns associated with multi-tenant cloud FPGAs, provides a comprehensive overview of the related security, privacy and trust issues, and discusses forthcoming challenges in this evolving field of study.

The ever-growing demand for intelligent devices capable of visual processing in real time at the edge requires a paradigm shift in computing architectures. Near-sensor computing offers a promising solution by bringing computation closer to the data source, enabling faster response times and reduced power consumption. However, traditional monolithic chip design struggles to meet the efficiency and flexibility demands of near- sensor visual intelligence tasks. This Ph.D. project investigates the transformative potential of chiplet interfaces in revolutionizing near-sensor computing for on-device visual intelligence. Chiplet technology offers a modular approach that enables the integration of heterogeneous cores and specialized hardware accelerators into a single package. Using this modularity, the project aims to achieve the following key objectives: (1) design and explore novel chiplet interface architectures, (2) hardware-software co-design for chiplet-based near-sensor processing targeting visual data, (3) power efficiency exploration and finally real-world application validation. The successful completion of this Ph.D. project is expected to yield significant contributions to the field of near- sensor computing. With expectations of proposing some novel chiplet interfaces for efficient visual on-device intelligence, the project has the potential to pave the way for a new generation of intelligent devices capable of real-time visual processing at the edge, with minimal reliance on cloud-based resources.

This abstract proposes a lightweight near-sensor image preprocessor for video data. The hardware system design targets low-power devices with constrained power and hardware resources. Our approach is a two-stage hierarchical architecture consisting of saliency-based generators that feed a saliency filter. Preliminary results demonstrated significant energy and hardware optimization compared to previous work in this field. Specifically, the proposed architecture uses 0.24%, 0.60%, and 9% of the total processing elements used by examined related work. Similarly, the total on-chip power usage of 0.686W, which is 34.5 % and 5.3% less for the same baseline. This motivates the integration of our near-sensor logic into a system where a high-level algorithm can benefit from data filtering.