EDBT 2026 Demo / reviewers in the wild / expert
Cao Wan
dblp:386/8687
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4ranked-venue papers
0as first author
4since 2021 · last 2026
0000-0001-7094-606XORCID · corroborated
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 4 · 4 since 2021
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2026 | Piecewise Linear Ultra-Wideband Chirp Generators for Sub-THz FMCW Radar in 28-nm CMOS
Yange Wang, Xinyu Ren, Cao Wan, Hanjun Jiang, Yuanjin Zheng |
ISCAS | 3 |
| 2025 | A mm-Wave Coupler-based Dual-band Power Amplifier for Advanced Driver Assistance SystemsabstractThe growing demand for high-performance components in wireless communication and automotive systems, especially for radar applications, has driven the need for dual-band power amplifiers (PAs) operating at 60GHz and 77GHz. These frequency bands are particularly beneficial for automotive radar systems, integral to Advanced Driver Assistance Systems (ADAS) and autonomous driving technologies, as they offer enhanced resolution, reduced interference, and faster data transmission rates. This paper presents the design and development of a dual-band PA based on a novel coupled-line dual-frequency matching structure. The PA’s innovative input and output matching networks utilize a unique coupler design to achieve simultaneous impedance matching at both 60GHz and 77GHz. Through comprehensive simulation, optimal matching impedances for both frequencies were identified, enabling the PA to achieve an output power of 12 dBm at 60GHz and 10 dBm at 77GHz, with power-added efficiencies of 24.4% and 13.85%, respectively. The design also incorporates a two-stage power amplifier configuration that ensures high efficiency and gain across the dual bands. Experimental validation was performed using a small-signal test system, demonstrating excellent performance, with a peak power gain of 12.4 dB at 60GHz and 9.8 dB at 77GHz. This dual-band PA design is particularly well-suited for integration into automotive radar systems, thanks to its compact size, high power efficiency, and ability to support wideband matching. Furthermore, this work presents a highly efficient, wideband solution for next-generation automotive radar and communication systems operating in the millimeter-wave frequency range. Zhongzhiguang Lu, Yanshu Guo, Yange Wang, Cao Wan, Guanghao Fan, Yuanjin Zheng |
ISCAS | 4 |
| 2025 | Compact Sub-THz Frequency Conversion Module in 28-nm CMOS for D-Band Radar TransceiverabstractThis paper proposes a compact sub-THz frequency conversion module for D-band transceivers, fabricated using a 28-nm CMOS process. The module integrates an injection-locked frequency multiplier (ILFM) for Tx signal frequency up-conversion and an active Gilbert double-balanced mixer for Rx signal frequency down-conversion. The system was tested on a probe station. Utilizing a tunable coupling-coil technique and optimized inductance, the ILFM achieves a locking range of 105.2-125.5 GHz with an output power of -4.5 dBm. The Gilbert mixer demonstrates a conversion loss of -6.5 dB across the same range with an LO power of -4.2 dBm. The active region of ILFM and mixer chips occupy areas of 0.31 mm2and 0.51 mm2, respectively. Yange Wang, Guanghao Fan, Boyi Dong, Zhongzhiguang Lu, Cao Wan, Yuanjin Zheng |
ISCAS | 5 |
| 2025 | A "2 + 1" Cores Triple-Mode OscillatorabstractThis paper proposes a millimeter-wave (mmW) oscillator with “$2+1$” cores and triple operation modes to realize an octave-tuning range. An auxiliary core, comprising a switch and a negative transconductance cell, is introduced to the regular dual-core oscillator to generate a third mode with enhanced effective Q. This auxiliary core not only broadens the tuning range without compromising phase noise or chip area but also avoids the risk of introducing mismatch into two regular cores like triple-core oscillators. The demand for low interconnect resistance is relieved because of the merits of less core mismatch and extra magnetic injection lock path. The behavior of the proposed oscillator in different modes is studied analytically. A quantitative analysis of phase noise and interconnect resistance in the dual-core oscillator is presented and verified against circuit simulations. Implemented in a 65-nm CMOS process, the oscillator achieves a 72.24% tuning range from 16.35 to 35.48 GHz and a peak figure-of-merit of tuning range and area (FoM$_{\mathrm {TA}}$) of -217.07 dBc/Hz at 20.27 GHz with 1 MHz frequency offset. The chip operates from a 1 V supply with a power consumption from 6.3 to 21.76 mW and a core area of 0.075 mm2. Shuai Deng, Pei Qin, Taotao Xu, Cao Wan, Xiongyao Luo, Wenquan Che, Quan Xue |
IEEE Trans. Circuits Syst. I Regul. Pap. | 5 |