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Yeonggeon Kim

dblp:386/9846 · DBLP profile ↗
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3ranked-venue papers
1as first author
3since 2021 · last 2025
0009-0008-4876-6108ORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 3 · 1 first-author · 3 since 2021Applied, interdisciplinary, general and emerging computing · 1 · 1 first-author · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Hardware accelerators and domain-specific architectures · 100%

Topics — the 3 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Hardware accelerators and domain-specific architectures › machine learning accelerator › neural network accelerator
diffusion model accelerator
0.912025
RADiT: Redundancy-Aware Diffusion Transformer Acceleration Leveraging Timestep Similarity · DAC 2025
Hardware accelerators and domain-specific architectures
machine learning accelerator
0.912025
RADiT: Redundancy-Aware Diffusion Transformer Acceleration Leveraging Timestep Similarity · DAC 2025
Hardware accelerators and domain-specific architectures › machine learning accelerator
transformer accelerator
0.912025
RADiT: Redundancy-Aware Diffusion Transformer Acceleration Leveraging Timestep Similarity · DAC 2025

Methods — techniques the papers use, named apart from their topics

timestep similarity reuse · 0.9redundancy detection · 0.9dynamic threshold scaling · 0.9
YearPublicationVenuePosition
2025 RADiT: Redundancy-Aware Diffusion Transformer Acceleration Leveraging Timestep Similarity
abstract
Diffusion Transformers (DiTs) have demonstrated unprecedented performance across various generative tasks including image and video generation. However, a large amount of computations on the inference process and iterative sampling steps in the DiT models result in high computational costs, leading to substantial latency and energy consumption challenges. To address these issues, we propose a redundancy-aware DiT (RADiT), a novel software-hardware co-optimization accelerator for DiTs that minimizes redundant operations in the iterative sampling stages. We identify data redundancy by evaluating blockwise input features and skip redundant computations by reusing results from consecutive timesteps. Furthermore, to minimize accuracy degradation and maximize computational efficiency, the Dynamic Threshold Scaling Module (DTSM) and Compress and Compare Unit (CCU) are employed in the redundancy detection process. This approach enables DiTs to achieve up to $1.8 \times$ and $1.7 \times$ faster speeds for image and video generation, respectively, without compromising quality, along with 41% and 45.5% reductions in energy consumption. Our RADiT scheme improves throughput by $1.67 \times$ and $1.76 \times$ for image and video generation tasks, respectively, while maintaining output quality and significantly reducing energy consumption.
Youngjun Park, Yeonggeon Kim, Gisan Ji, Sungju Ryu
DAC3
2025 OptiRange: An Efficient ReRAM-Based PIM Accelerator with ADC Resolution Optimization
abstract
Processing-in-memory (PIM) techniques have attracted significant attention in computer architecture research due to their ability to mitigate the memory wall bottleneck for deep neural network (DNN) applications. In-memory computing (IMC) using ReRAM crossbar arrays is promising for energy efficiency but suffers from high-cost peripheral circuits, particularly analog-to-digital converters (ADCs). There are existing methods to reduce ADC energy consumption, such as lowering resolution or sharing an ADC among multiple columns. Unfortunately, these techniques reduce throughput. In this work, we propose OptiRange for PIM accelerators that enhances both energy efficiency and throughput while maintaining accuracy and model flexibility. OptiRange proposes a split-the-burden (STB) algorithm that manipulates crossbar cell values without changing the weights. STB reduces large cell values, shifts the column-sum distribution center closer to zero, and minimizes the number of low-resistance state (LRS) cells, significantly lowering the hardware-level fixed ADC resolution and improving accuracy. Furthermore, OptiRange utilizes dynamic ADC range (DAR) adaptation, determining the optimal ADC operating range per column at the software level and enabling the skipping of redundant ADC conversion cycles at runtime. An associated ADC range-based grouping (AG) strategy leverages the resulting dynamic latencies to manage synchronization and further boost system throughput. By combining weight-preserving cell manipulation with adaptive ADC operation and synchronization, OptiRange dynamically optimizes the ADC workload. Experimental results indicate that our method significantly enhances overall performance compared to conventional ReRAM-based accelerators.
Sangkyu Jeon, Gisan Ji, Yeonggeon Kim, Youngjun Park, Sungju Ryu
ICCAD3
2024 Statues: Energy-Efficient Video Object Detection on Edge Security Devices with Computational Skipping
abstract
This paper proposes a software and hardware co-optimization method tailored to object detection on edge security devices. Object detection on video inputs requires a massive number of MAC computations, so it is difficult to implement a real-time inference task with limited computational budget on edge security devices. To relieve such computational complexity, we propose a Statues, selective computational skipping approach by scoring pixel differences in the recent inputs. If the score is low enough, we skip the rest DNN part because we expect the almost same object detection result as the previous frame. Our Statues approach maximizes energy-efficiency by 44% compared with the conventional method with negligible accuracy drop.
Yeonggeon Kim, Sungju Ryu
ISLPED1