As 3-Dnandflash memory continues to scale toward higher density, significant reliability disparities arise among different pages in triple-level cell (TLC) flash, posing severe challenges to error-correction codes (ECCs) in the middle and late stages of flash lifetime. Polar codes have been introduced into flash storage systems due to their near-capacity performance; however, their decoding heavily relies on the accuracy of log-likelihood ratios (LLRs). Hard-decision sensing in flash memory leads to severe loss of soft information, thereby limiting the achievable error-correction performance. To address these challenges, this article proposes a page-aware reliability optimization scheme for polar codes in 3-D TLC flash memory. First, a page-aware polar bit mapping (PA-PBM) scheme is proposed, which exploits the mismatch between polar bit importance and page reliability by mapping critical bits to highly reliable pages and frozen bits to less reliable pages, thereby reducing the probability of critical errors. Building upon PA-PBM, a reliability-aware weighted polar mapping (RAW-PM) scheme is further developed, which incorporates page-level raw bit error rate (RBER) information to construct confidence-differentiated pseudo-soft LLRs and refines the bit mapping strategy, enabling weighted path metric (PM) correction and improving decoding accuracy under hard-decision sensing. Extensive experiments are conducted on a flash memory test platform to evaluate the proposed schemes. The results demonstrate that RAW-PM significantly improves the frame error-correction success rate in the middle and late stages of flash lifetime and reduces the post-ECC uncorrectable bit error rate (UBER) by more than one order of magnitude. Under typical large-scale access, RAW-PM introduces no additional read operations, requires no changes to the decoder architecture, and achieves these gains with minimal control and computational overhead, demonstrating excellent practical feasibility.

Three-dimensional (3-D)nandflash memory has emerged as the predominant solution for high-capacity nonvolatile data storage. However, the continuous increase in storage density has concurrently led to significant challenges in data reliability degradation. This article investigates the application of polar codes for error correction innandFlash memory. We propose a combined Monte Carlo (CMC) method to dynamically determine information bit positions in polar code encoding for flash memory chips under varying reliability statuses. For decoding, we identify that the hard-decision read mechanism in flash memory introduces extreme log-likelihood ratio (LLR) quantization effects. This quantization phenomenon may erroneously prune correct decoding paths during successive cancellation list (SCL) decoding, thereby degrading the error correction capability of polar codes. To address this critical issue, we develop a cascaded parity-check (PC)-assisted path pruning scheme integrated with the SCL algorithm. The experimental results demonstrate that the proposed polar code algorithm can significantly enhance the reliability of data storage innandflash memory. In the long code length scenario, the proposed polar decoding scheme with PC-assisted pruning achieves a maximum uncorrectable bit error rate (UBER) reduction of 98.62% compared to algorithms without PC. The proposed approach demonstrates an 8.56 times increase in the raw bit error rate (RBER) threshold for achieving 100% error correction success, significantly surpassing the performance of conventional low-density parity-check (LDPC) codes, especially toward the end of the flash memory’s lifespan.

Low-density parity-check (LDPC) codes are now broadly employed as error correction code (ECC) solutions in NAND flash memories. With the rapid development of high-performance three-dimensional (3-D) NAND memories, mitigating the read latency caused by LDPC decoding attempts has emerged as an investigation focus. Existing investigations have demonstrated that efficient memory sensing is crucial to enhancing the efficiency of LDPC decoding attempts. The optimal memory sensing parameter options are determined by the threshold voltage distributions of NAND flash, which are difficult to be dynamically extracted during data retention. To address the issue, this article proposes an online lightweight strategy for threshold voltage distribution estimation, named LVDE. LVDE suggests a probe wordline design that uses one-read sampling to measure the threshold voltage distributions during long-term retention. Further, LVDE develops a methodology for the cross-layer estimation of threshold voltage distributions, thereby utilizing the measurements of the probe wordline to estimate those of each layer. LVDE is implemented on real flash chips to compare with numerous state-of-the-art strategies. Experimental results demonstrate that LVDE can significantly enhance the efficiency of LDPC decoding attempts and thus improve the read performance of 3-D NAND flash memory.

To enhance the reliability of 3-D TLC NAND flash memory, low-density parity-check (LDPC) codes have become widely adopted. However, as the number of read, program or erasures increases, the raw bit error rate (RBER) of read data in flash memory chips also rises, leading to the challenge of increased LDPC decoding latency. To address this, an idea of utilizing the decoding correct probability of LDPC to reduce latency is proposed. First, by analyzing the encoding method of TLC NAND flash memory, a single direction characterization error model based on the correlation between individual pages is constructed. Next, through experimental validation, the feasibility of using the number of iterations as an indicator of decoding correct probability is demonstrated, leading to the proposal of a low-overhead and high-performance Iterative Alternative Correct Probability Optimization (IACPO) scheme. Leveraging the fact that LDPC decoding exhibits a high success probability within a specific range of read data, the existence of successful decoding area (SDA) is confirmed through a large number of real experiments, and the distribution characteristics of SDA in TLC NAND flash memory are analyzed. Finally, the Utilizing LDPC Decoding Correct-Probability Optimization (ULDCO) scheme to further optimize latency is proposed. This scheme uses SDA to improve the probability of correct data reading, particularly in the middle and later stages of flash memory life, in combination with the IACPO scheme. Experimental results show that the proposed IACPO and ULDCO schemes are not only generally applicable but also achieve significantly iterative latency reduction by 73.43% and 81.51%, respectively, compared to traditional schemes, with negligible storage and computation overhead. These results clearly demonstrate the superior performance of the proposed schemes in reducing iteration latency.

The low-density parity-check code (LDPC) has been widely used to significantly enhance the reliability of 3-D NAND flash memory. However, in cases where the raw bit error rate (RBER) of the data is high, it not only demands more sense levels but also requires a large number of iterations, leading to a notable read latency issue. To mitigate this challenge, this paper introduces an innovative lightweight latency decrease (LLD) scheme. Initially, by examining the correlation between the number of iterations and the hard decision level (HDL), a functional model that encapsulates the relationship between iteration and offset is established. Building upon this model, the all-wordlines latency decrease (AWLD) scheme is proposed. In an effort to further decrease latency, an in-depth analysis of the similarities among different wordlines within a flash memory block is conducted, leading to the development of an optimized one-wordline lightweight latency decrease (OWLLD) scheme. For scenarios involving random reading of small data volumes, the interplay between function models of various overlapping regions is delved into, which ultimately results in the proposal of a further optimized one-page lightweight latency decrease (OPLLD) scheme. Experimental findings reveal that the OPLLD scheme can enhance the iterative performance of LDPC by up to 94.63% and reduce latency by up to 66.89% compared to traditional algorithms, while incurring minimal storage and computational overhead. This clearly indicates that the proposed scheme substantially enhances the read latency performance of LDPC in flash memory.