EDBT 2026 Demo / reviewers in the wild / expert
Shuiyi He
dblp:387/5730
· DBLP profile ↗
4ranked-venue papers
2as first author
4since 2021 · last 2026
0009-0008-7112-6045ORCID · corroborated
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 4 · 2 first-author · 4 since 2021Software engineering, systems software and programming languages · 2 · 2 since 2021
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2026 | From Memorization to Generalization: A Practical Neural Network Prefetching Framework
Zicong Wang, Shuiyi He, Dezun Dong, Xiangke Liao |
ISCA | 3 |
| 2025 | Amphi: Practical and Intelligent Data Prefetching for the First-Level CacheabstractData prefetchers play a crucial role in alleviating the memory wall by predicting future memory accesses. First-level cache prefetchers can observe all memory instructions but often rely on simpler strategies due to limited resources. While emerging machine learning-based approaches cover more memory access patterns, they typically require higher computational and storage resources and are usually deployed in the last-level cache. Other intelligent solutions for the first-level cache show only modest performance gains. To address this, we propose Amphi, the first practical and intelligent data prefetcher specifically designed for the first-level cache. Applying a binarized temporal convolutional network, Amphi significantly reduces storage overhead while maintaining performance comparable to the SOTA intelligent prefetcher. With a storage overhead of only 3.4 KB, Amphi requires only one-eighth of Pythia's storage needs. Amphi paves the way for the broader adoption of intelligence-driven prefetching solutions. Zicong Wang, Shuiyi He, Dezun Dong, Xiangke Liao |
DATE | 3 |
| 2025 | Elevating Temporal Prefetching Through Instruction Correlation
Shuiyi He, Zicong Wang, Dezun Dong, Liquan Xiao |
MICRO | 1 |
| 2024 | Chimera: Leveraging Hybrid Offsets for Efficient Data PrefetchingabstractData prefetching is an essential technique in contemporary high-performance processors for mitigating the effects of long-latency memory accesses. With the increasing demand for prefetcher to learn complex memory access patterns, many state-of-the-art prefetchers adopt methods such as using the program counter or access delta to separate memory access streams. This allows them to learn detailed memory access features and thereby improve memory system performance. However, the separation-based approach is prone to missing global correlations, leading to miss prefetching opportunities. In this paper, we propose Chimera, a hybrid offsets prefetcher that captures multiple offset features from the overall stream of memory access instructions, thus overcoming the drawbacks of traditional prefetchers that tend to lose memory access information when learning from one-sided features. We evaluated Chimera using SPEC CPU 2006 and 2017 through simulation, and the results show that Chimera improves system performance by 39.5% over a baseline with no data prefetcher and by 6.6% over the state-of-the-art data prefetcher. Shuiyi He, Zicong Wang, Qiyao Sun, Dezun Dong |
PACT | 1 |