This work presents a Resistive RAM (RRAM)-based Ising machine characterized by high spin density and efficient analog in-memory computing. The proposed design enables compact spin representations that support interactions with up to eight neighboring spins at 1-bit precision. The functionality and performance of the proposed Ising machine is evaluated using comprehensive simulation in 28nm CMOS technology, incorporating measured RRAM variation characteristics to validate its robustness and efficiency. Additionally, software-based simulations are employed to solve classical combinatorial problems, such as the Max-Cut problem, while accounting for the non-idealities inherent in the proposed RRAM-based analog in-memory computing approach. Each proposed spin occupies an area of 13.5 μm2, achieving an area reduction of 16.7% to 92.1% compared to recent works, based on feature size normalization.

In the conventional RRAM design, differential reading for odd and even bitlines (BLs) facilitates high-speed data retrieval, but this comes at the cost of area overhead due to additional multiplexers, and is prone to causing performance degradation with inaccurate timing signals. In this work, a high performance RRAM macro is presented to solve the above problems through: 1) a compact dual-wordline (WL) array structure that splits the WLs into odd and even pairs, the inactive half of the BLs can be used as differential input without the extra multiplexers, thereby improving the storage density and reducing WL switching power consumption by 45%; 2) a replica BL control circuit to effectively track the BL discharge characteristics and accurately control WL pulse width, thus lowering read energy consumption and latency. A 1Mb RRAM macro with 64-bit bandwidth and 8.85Mb/mm2storage density is implemented using 28nm process, achieving a 3.5ns read cycle and consuming 9fJ per bit during reads, with the FoM (read throughput / area) at least 3.6× higher than prior works.

In recent years, Ising machines have emerged as a promising hardware solution for tackling combinatorial optimization problems (COPs). However, existing Ising solvers, whether based on discrete-time or continuous-time approaches, often face challenges in balancing solution quality, scalability, and computational speed. Discrete-time solvers typically suffer from slow convergence due to the sequential nature of spin updates, while continuous-time solvers often lack effective annealing mechanisms, limiting their solution accuracy. To address these limitations, this work proposes a novel architecture that integrates a differential Resistive Random Access Memory (RRAM) cell-based Ising design with a Randomized Granular Update (RAGU) method. This approach enhances scalability to larger spin systems while maintaining robust performance against circuit non-idealities and device variations. Additionally, an adaptive bitline (BL) voltage clamper is incorporated into the read path to limit current magnitudes, significantly improving power efficiency. A key feature of the RAGU method is its ability to naturally introduce randomness during the update process through coarse-grained updates, serving as an imprecise but effective sampling mechanism. This innovation not only accelerates convergence and improves the system’s ability to escape local minima but also ensures high solution quality. Extensive simulations and experiments on randomly weighted graphs with varying densities demonstrate that the proposed architecture consistently achieves near-optimal solutions ($>$96%) while drastically reducing the time-to-solution to as low as 0.6$\mu$s.

The neuromorphic system aims to implement large-scale spiking neural networks (SNN) through hardware, ultimately achieving human-level intelligence. At this stage, it is difficult for a single silicon-based chip to reach the density of the human brain, so it is important to improve the area efficiency of neuromorphic chips. We present a novel neuromorphic hardware that employs high area-efficiency chain RRAM synaptic array, and compact RRAM-based neurons. The proposed chain RRAM structure achieves a small cell size of 41.5F2 at 28 nm logic process. Compared to the conventional 1T1R structure, the chain structure has a 22.2% area reduction and a 58.8% parasitic capacitance reduction. As for the neuron design, we use RRAM instead of the capacitor to integrate membrane voltage. To alleviate the endurance issue of RRAM, we propose an (anti-) integration scheme that removes the operation of membrane voltage reset. The simulation results demonstrate an average energy consumption of 1.15pJ per spike and an area of$15.9\mu $m2. With the (anti-)integration scheme, the RRAM’s lifetime is demonstrated to extend by$2\times $and the energy of programming RRAM is demonstrated to be reduced by$2\times $.