Assessment management in large‑enrollment microelectronics laboratory courses places a substantial administrative burden on graduate teaching assistants (GTAs), who must aggregate scores across multipart deliverables, apply class‑wide curves, roll extra credit into summative grades, enforce score caps, and post results to the Learning Management System (LMS). The prevailing approach exporting a gradebook CSV from Canvas, editing it in a spreadsheet, and re‑importing is serial, introduces manual transcription steps well documented to produce errors, and offers no guarantee against silent data loss caused by Canvas’s fragile column‑matching import rules. We present Score‑Reflow, a Python‑based GUI that communicates directly with the Canvas LMS REST API, replacing the CSV loop with a single‑click, auditable pipeline, while also significantly improving grading accuracy and traceability for large courses. Score‑Reflow implements a generalized bounded‑additivity model that subsumes five assessment‑workflow patterns common in hardware labs: (1) uniform class curve, (2) extra‑credit roll‑up, (3) multipart aggregation, (4) bounded curve‑and‑cap, and (5) cross‑name-space resolution of Canvas quiz and assignment identifiers. Deployed in a required four‑credit ECE course serving 175 students across six lab sections, Score‑Reflow reduces a multi‑hour grading event to minutes, enforces consistent treatment across sections, and returns GTA time to direct instructional engagement that advances laboratory learning outcomes.

We present Compression-Based Feature Clustering (CBFC), a low-footprint FPGA accelerator for training-free similarity inference in hybrid LLM pipelines. CBFC replaces the un-synthesizable gzip compressor with a fully HLS-synthesizable, fixed-resource LZ77 engine returning the deterministic scalar compressed lengths required by Normalized Compression Distance (NCD) k-NN classification. On a Zynq UltraScale+ at 300 MHz, CBFC achieves up to 3.41 × speedup over CPU gzip (70.6% latency reduction) while consuming only 2-12% of on-chip resources, leaving ample headroom for replication or co-location with other accelerator datapaths. Classification accuracy is on par with gzip across standard text benchmarks.

Teaching the fundamentals of Register-Transfer Level (RTL) digital hardware design presents many unique challenges in classroom and laboratory settings. Hardware Design Language (HDL) requires students to reason about clock cycles, concurrency, and hardware architecture. Each of these new concepts presents significant new learning hurdles for undergraduate students. Sufficiently engaging learners throughout project assignments presents a challenge for instructors as feedback cannot be scaled effectively due to time constraints and complexity of RTL design. To address this, we develop RTL-SMARTIE, an instructional technology which evaluates RTL submissions and generates immediate feedback using Large Language Model (LLM) agents. The system processes student submissions and provides design suggestions and debugging guidance. The iterative nature of this tool serves as a critical bridge missing from current methods that are not structured for RTL reasoning. Foundational digital logic designs, ranging from a counter to a full UART transmitter and receiver, are used as test cases for evaluation of agent-generated feedback and resulting student score improvements. Across several iterations, RTL-SMARTIE boosts the ability of student surrogates to reason about correct RTL, with score improvements upwards of 20% observed across low-performing student submissions.

State-of-the-art image classification systems utilize powerful machine-learning-based tools such as Convolutional Neural Networks (CNNs). These networks can achieve high recognition accuracies, but suffer from a black-box problem where the inner workings are incomprehensible by humans that seek to use them. In this paper, a Feature-Oriented Cellular Automata Learning (FOCAL) system is developed to extend traditional gradient-filter-based methods by implementing a Cellular Automata (CA) reasoner utilizing rule-based primitives for determining mutual agreement between neighboring pixels. This novel method is demonstrated to identify features more accurately than standard filter methods and produce classification results that are competitive with typical CNNs, while also allowing a-priori definition of important features facilitating explainable feature classification decision processes. Experiments spanning a variety of influential factors indicate that rebaselining and normalization are vital to the success of the CA-based approach. Furthermore, within certain models, the use of CA is shown to reduce computational demand by over 90% while incurring only a 2% reduction in classification accuracy. Finally, the scalability of the FOCAL system is investigated using the CIFAR-10 dataset and contemporary Deep Neural Networks, and shown to encourage promising avenues of research into explainability while reducing computational processing demands.