EDBT 2026 Demo / reviewers in the wild / expert
Doohyun Yoon
dblp:388/9080
· DBLP profile ↗
1ranked-venue papers
0as first author
1since 2021 · last 2025
0009-0006-7037-8318ORCID · reported
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1 · 1 since 2021
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Electronic design automation · 100% |
Topics — the 3 heaviest of 3, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Electronic design automation
hardware verification and test |
0.9 | 1 | 2025 | An Efficient Test Scheduling Method Based on Dynamic Pairing · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2025 |
Electronic design automation › hardware verification and test
system-on-chip testing |
0.9 | 1 | 2025 | An Efficient Test Scheduling Method Based on Dynamic Pairing · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2025 |
Electronic design automation › hardware verification and test
test scheduling |
0.9 | 1 | 2025 | An Efficient Test Scheduling Method Based on Dynamic Pairing · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2025 |
Methods — techniques the papers use, named apart from their topics
heuristic algorithm · 0.9dynamic pairing · 0.9
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2025 | An Efficient Test Scheduling Method Based on Dynamic PairingabstractTest scheduling is a process that manages tests within a System-on-Chip (SoC) to minimize test time by allocating test resources and adjusting priorities. Efficient test scheduling offers cost saving opportunities by reducing test time without compromising test coverage. Since test scheduling is a NP-hard problem, conventional methods adopt optimization or heuristic algorithms that leverage metrics of each test. However, due to the interdependence of tests based on how limited resources are allocated, finding the optimal solution to minimize test time is challenging. In this article, a dynamic pairing algorithm is proposed to consider the mutual influence of tests on each other in the test scheduling process. The proposed method identifies the available test resources for a specific pair and minimizes the test time of the paired modules under identified constraints. Additionally, the proposed algorithm employs a heuristic-based approach to test scheduling to reduce the CPU time needed for scheduling. The proposed heuristic algorithm sequentially schedules test target modules and determines the optimal test schedule through dynamic pairing. Experiments have been carried out on diverse benchmarks and under various constraint conditions. The results indicate that the proposed method achieves shorter test times on average in comparison to conventional methods. Heetae Kim, Hyojoon Yun, Doohyun Yoon, Sungho Kang 0001 |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. | 3 |