With the increasing number of I/O pins in highly integrated semiconductor products, semiconductor packaging has become an essential yet complex part of integrated circuit (IC) design. The substrate plays an important role in advanced semiconductor packaging and provides the chip with electrical connections and heat dissipation. While numerous studies have addressed the substrate routing problem, only one state-of-the-art work provides a customized routing flow specifically designed for packages with wire-bonding style and fine-pitch ball grid arrays (FBGA), which are more widely used than advanced packaging due to their maturity and lower cost. However, the existing router suffers from unsatisfactory routability due to its simplistic implementation and lack of necessary consideration for finger connections. Therefore, this paper proposes several optimization heuristics, such as finger accessibility enhancement, progressive rerouting, and half-grid rerouting techniques, to further improve the overall routing completion rate. Experimental results show that the proposed heuristics are capable of avoiding routing resource wastage, achieving better routing quality, and eliminating design-rule violations.

As an important intermediate between integrated circuits (ICs) and the printed circuit board (PCB), the routing in the package substrate plays a crucial role in the efficiency and accuracy of signal and power transmission. While numerous research efforts have focused on substrate routing to avoid inefficient, time-consuming, and error-prone manual processes, few of them have addressed the challenge of routing multi-pin nets, particularly those with a large number of pins. This article presents a three-stage framework of multi-pin net routing for packages with fine-pitch ball grid arrays, consisting of pin grouping, minimum spanning tree topology generation, and group topology connection. Our framework classifies net connections into different categories, prioritizes their routing ordering, and applies different routing approaches and strategies to boost overall routability. The results of the experiments conducted on six real industrial designs demonstrate that our framework can simultaneously and effectively handle two-pin nets and multi-pin nets with better routing performance compared to the state-of-the-art work.

Wire bonding is a mature packaging technique that enables chip pins to transmit signals to bonding fingers on the substrate through bonding wires. Such commodity technology is also essential in supporting the rapid development of the system in package and heterogeneous integration technologies. However, the automation tools are relatively deficient compared to other packaging techniques, resulting in tremendous manual design time and engineering effort due to numerous wire-bonding design constraints. This paper addresses the finger placement problem and serves as the first work considering the orientation constraint of fingers. The finger placement flow is divided into three stages. First, an integer linear programming (ILP) formulation is developed to allocate each net finger row. After that, we utilize mixed-integer quadratic programming (MIQP) to place the bonding fingers and consider the wire crossing constraint. Finally, the locations of the bonding finger are refined by considering both the bonding finger orientation angle and the finger spacing constraints. The final layouts generated by our integrated finger placement and substrate routing framework outperform manual designs in terms of the design time, the total wirelength, and the routing completion rate.

Traditional packaging routers are typically limited to 90- and 135-degree routing angles. However, with the advancement in advanced packaging technologies and the increasing demand for a higher number of I/Os, any-angle routing has become a promising solution thanks to its ability to explore a larger solution space and reduce overall wirelength. Therefore, we proposed an any-angle routing framework for die-to-substrate connections. First, the proposed routing graph enables accurate estimation of routing resource utilization in the global routing stage. After the global routing stage, we introduce two wire-length optimization strategies: (1) a concurrent adjustment of access points to reduce total wirelength by considering all nets simultaneously, and (2) a dynamic programming-based method to minimize the number of wire segments in each single net. Experimental results demonstrate that our two-stage refinement strategies achieve superior routing quality compared to the global routing result.