As a core arithmetic operation and security guarantee of Fully Homomorphic Encryption (FHE), Number Theoretic Transform (NTT) of a large degree is the primary source of computational and time overhead. In this paper, we propose a scalable and conflict-free memory mapping algorithm that breaks the memory bound and releases a large amount of on-chip resources. A flexible and no-stall hardware/software pipeline architecture is designed to boost the throughput of NTT/INTT of N = 216 to over 48,543 operations per second with area efficiency, which 4× and 10× speed up the FPGA-based (HPCA'23) and GPU-based (HPCA'23) schemes.

Fully Homomorphic Encryption (FHE) enables computations directly on encrypted numbers, thereby preserving the privacy of sensitive information even in untrusted environments. However, the substantial computational overhead associated with homomorphic evaluations restricts the practical application of FHE schemes. To deal with the performance challenges, this paper proposes a hardware/software pipeline framework with a three-level cache architecture to accelerate the costly Key-Switching operation in FHE. This framework supports the dynamically reconfigurable processing mode, two parallelism strategies, and flexible control flow, effectively breaking the compute-bound and the memory-bound limitations. A no-stall and conflict-free memory mapping algorithm is implemented on the Xilinx U55C FPGA platform that boosts the throughput of ciphertext-ciphertext multiplication to 395 operations per second, which 1.4× and 2.5× speeds up the FPGA-based (HPCA'23) and GPU-based (HPCA'23) schemes with the same parameter set and precision.