Clustering single-bit flip-flops (SBFFs) into multi-bit flip-flops (MBFFs) effectively reduces power and area. However, excessive displacement during the clustering and legalization process may incur significant timing degradation. To address this issue, we propose the first comprehensive MBFF placement methodology that addresses excessive displacement caused by pre-placed cells during clustering and legalization while simultaneously optimizing timing, power, area, and bin utilization. Our methodology includes three main features: (1) a force model to relocate flip-flops and reduce timing violations, (2) a clustering and legalization process to reduce timing degradation caused by displacement, and (3) a multi-objective function to identify flip-flop candidates suitable for MBFF clustering. Our methodology outperforms all participating teams in the 2024 CAD Contest at ICCAD on Power and Timing Optimization Using Multi-Bit Flip-Flops, based on exactly the same settings.

This paper presents the first performance-driven pre-assignment routing algorithm for high-speed package designs. The proposed algorithm guarantees the minimum critical path length while preventing wire crossings within a single metal layer. A novel dynamic programming-based method is introduced to efficiently generate a high-quality baseline routing solution, allowing early termination in the subsequent search stage. Then, an efficient search-based method with effective pruning techniques is developed to optimally arrange all nets’ physical routing order, ensuring the minimum critical path length while avoiding suboptimal search branches. The proposed algorithm achieves a 32.9% reduction in the critical path length with only a 0.6% increase in the total path length compared with the previous work across five industrial designs. Furthermore, the proposed search-based method completes the largest design with more than 1000 nets in less than 1.6 seconds, delivering a 5000× speedup over exhaustive branch-and-bound methods while preserving optimality.

This paper proposes a mixed-size 3D analytical placement framework for face-to-face stacked integrated circuits fabricated with heterogeneous technology nodes and connected by hybrid bonding technology. The proposed framework efficiently partitions a given netlist into two dies and optimizes the positions of each macro, standard cell, and hybrid bonding terminal (HBT). A multi-technology objective function and a multi-technology density penalty calculation process are adopted to handle the heterogeneous-technology-node constraints during mixed-size 3D global placement. Furthermore, a 3D objective function is used to refine the placement result during HBT-cell co-optimization. Our placer achieves the best results for all contest test cases compared with the participating teams at the 2023 CAD Contest at ICCAD on 3D Placement with Macros.