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Chase Szafranski

dblp:389/7290 · DBLP profile ↗
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1ranked-venue papers
0as first author
1since 2021 · last 2024
0009-0006-2782-0932ORCID · reported

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Hardware accelerators and domain-specific architectures · 100%
Artificial intelligence
1 paper
3D vision · 100%
Computer graphics and multimedia
1 paper
Virtual and augmented reality · 100%

Topics — the 3 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Computer vision › 3D vision
human mesh recovery
0.812024
VITA: ViT Acceleration for Efficient 3D Human Mesh Recovery via Hardware-Algorithm Co-Design · DAC 2024
Hardware accelerators and domain-specific architectures
algorithm-hardware co-design
0.812024
VITA: ViT Acceleration for Efficient 3D Human Mesh Recovery via Hardware-Algorithm Co-Design · DAC 2024
Hardware accelerators and domain-specific architectures › machine learning accelerator › transformer accelerator
vision transformer accelerator
0.812024
VITA: ViT Acceleration for Efficient 3D Human Mesh Recovery via Hardware-Algorithm Co-Design · DAC 2024

Methods — techniques the papers use, named apart from their topics

dataflow optimization · 2.3average pooling · 2.3
YearPublicationVenuePosition
2024 VITA: ViT Acceleration for Efficient 3D Human Mesh Recovery via Hardware-Algorithm Co-Design
abstract
Vision Transformers (ViTs) have emerged as a promising solution to enable efficient 3D Human Mesh Recovery (HMR) in augmented and virtual reality (AR/VR) applications. Despite many advancements in algorithm design, it remains a challenge to efficiently accelerate ViT-based HMR due to high computational complexity, substantial memory footprint, and compromised data locality. In this paper, we propose VITA, a hardware and algorithm co-design framework for ViT-based HMR with improved performance and energy efficiency. Specifically, on the algorithm side, we propose an average pooling model to replace conventional multi-head attention, which is further optimized with improved data locality. On the hardware side, we propose an accelerator architecture that can efficiently support various dataflows and computations demanded by pooling, normalization, and convolution operations. We evaluate the proposed VITA, and the evaluation result shows that the proposed VITA design can achieve 5.05× and 69.12× speedups on average over the state-of-the-art GPUs and CPUs on HMR tasks.
Shilin Tian, Chase Szafranski, Fan Yao 0001, Ahmed Louri, Chen Chen 0001, Hao Zheng 0005
DAC2