Andrew Friedley

dblp:39/10101 · DBLP profile ↗
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2ranked-venue papers
2as first author
0since 2021 · last 2013
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2 · 2 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
Parallel and multicore computing · 76% High-performance computing · 19% Processor architecture and microarchitecture · 6%

Topics — the 5 heaviest of 6, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Parallel and multicore computing › parallel programming models
distributed memory programming
0.212013
Ownership passing: efficient distributed memory programming on multi-core systems · PPoPP 2013
Parallel and multicore computing › parallel programming models
message passing
0.212013
Hybrid MPI: efficient message passing for multi-core systems · SC 2013
Parallel and multicore computing
parallel programming models
0.212013
Hybrid MPI: efficient message passing for multi-core systems · SC 2013
Parallel and multicore computing › parallel programming models
shared-memory parallelization
0.212013
Ownership passing: efficient distributed memory programming on multi-core systems · PPoPP 2013
Processor architecture and microarchitecture
chip multiprocessor
0.012013
Hybrid MPI: efficient message passing for multi-core systems · SC 2013

Methods — techniques the papers use, named apart from their topics

static analysis · 0.2shared memory communication · 0.2program transformation · 0.2MPI · 0.2
YearPublicationVenuePosition
2013 Ownership passing: efficient distributed memory programming on multi-core systems
abstract
The number of cores in multi- and many-core high-performance processors is steadily increasing. MPI, the de-facto standard for programming high-performance computing systems offers a distributed memory programming model. MPI's semantics force a copy from one process' send buffer to another process' receive buffer. This makes it difficult to achieve the same performance on modern hardware than shared memory programs which are arguably harder to maintain and debug. We propose generalizing MPI's communication model to include ownership passing, which make it possible to fully leverage the shared memory hardware of multi- and many-core CPUs to stream communicated data concurrently with the receiver's computations on it. The benefits and simplicity of message passing are retained by extending MPI with calls to send (pass) ownership of memory regions, instead of their contents, between processes. Ownership passing is achieved with a hybrid MPI implementation that runs MPI processes as threads and is mostly transparent to the user. We propose an API and a static analysis technique to transform legacy MPI codes automatically and transparently to the programmer, demonstrating that this scheme is easy to use in practice. Using the ownership passing technique, we see up to 51% communication speedups over a standard message passing implementation on state-of-the art multicore systems. Our analysis and interface will lay the groundwork for future development of MPI-aware optimizing compilers and multi-core specific optimizations, which will be key for success in current and next-generation computing platforms.
Andrew Friedley, Torsten Hoefler, Greg Bronevetsky, Andrew Lumsdaine, Ching-Chen Ma
PPoPP1
2013 Hybrid MPI: efficient message passing for multi-core systems
abstract
Multi-core shared memory architectures are ubiquitous in both High-Performance Computing (HPC) and commodity systems because they provide an excellent trade-off between performance and programmability. MPI's abstraction of explicit communication across distributed memory is very popular for programming scientific applications. Unfortunately, OS-level process separations force MPI to perform unnecessary copying of messages within shared memory nodes. This paper presents a novel approach that transparently shares memory across MPI processes executing on the same node, allowing them to communicate like threaded applications. While prior work explored thread-based MPI libraries, we demonstrate that this approach is impractical and performs poorly in practice. We instead propose a novel process-based approach that enables shared memory communication and integrates with existing MPI libraries and applications without modifications. Our protocols for shared memory message passing exhibit better performance and reduced cache footprint. Communication speedups of more than 26% are demonstrated for two applications.
Andrew Friedley, Greg Bronevetsky, Torsten Hoefler, Andrew Lumsdaine
SC1