Multistandard SoC's including advanced RF and analog circuitry with digital blocks are pervasive in modern IC's. However, the system design and verification methodologies that capture the complexity of multistandard RF SoC's are still limited. In this paper, an HDL design methodology is introduced for multistandard RF SoC's, which covers all the design layers from system design, to automatic extraction of the models from circuits and a systematic top level verification. The offered HDL based design methodology combines top down and bottom up design approaches, and brings the design and verification closer by reflecting the circuits to models automatically via an Automatic Parameter Extraction (APX) tool. System or block level verification is obtained with models automatically by overnight runs, without the need for extra test benches or designer interaction. This enables short term detection of functional errors or performance losses. A first time tape out of a multimode Bluetooth transceiver SoC is designed and fabricated in 8 months by using the offered methodology. The accuracy of the system level simulations show a very good match with the measurement results after fabrication. The test SoC is fabricated with 0.13 μm CMOS technology.

This paper describes a functional verification methodology for multi-standard wireless Systems-on-Chip (SoC) based on SystemC Virtual Prototyping (VP). The proposed semiautomatic pin-accurate RF VP generation method reduces huge handcrafting work to abstract circuitry into the event-driven simulation domain with satisfactory accuracy, while enabling the flexibility to choose different abstraction levels. A seamless transition between various signal abstractions is enabled by operator overload, e.g. passband and equivalent baseband in order to minimize simulation time according to test cases. This methodology is demonstrated for a low power RF transceiver with the achieved simulation speed of 500μs in 10s computation time.

This paper presents a novel demodulator architecture which significantly improves the receiver performance for continuous phase modulation (CPM) signals with low-effort and low-complexity design. A Viterbi algorithm (VA) based soft decision is implemented with multiple bits differential discriminator to fully utilize the dynamical range. The whole digital circuit is verified and synthesized in ASICs, and its BER performance against channel noise is measured through FPGA with the Bluetooth receiver chip. Compared to hard-decision and decision feedback equalizer (DFE) methods, measurement results show that the proposed demodulator gains a large advantage in Bluetooth Low Energy (LE) communications where power efficiency and implementation complexity are of primary concern.