Designing of arbiters has become increasingly important due to their wide use in the areas such as multi-processor systems-on-a-chip and on-chip or off-chip high-speed cross-bar switches and networks. In this paper, we proposed a new systematic model-driven flow for designing the new scalable multi-facet arbiters through a 3-phase process combined with the template-based modular design approach that includes the design model derivation phase, the architecture model (or template) design phase as well as the arbiter hardware implementation and generation phase. First, we described the phase 1 of the design flow of how to induce an arbiter design model in detail by careful analysis of arbiter design issues and systematic design space exploring the construction of the model. Then, we continue to discuss the phase 2 of how to derive an architecture model or template using the reusability, modularity and expansibility techniques. With both the design and the architecture models, designers can easily design or at least understand and thus choose many kinds of different but better arbiters efficiently. Finally, we have developed a scalable decentralized parallel tree structure and corresponding modular algorithms for efficient arbiter hardware implementation, which also is the final phase of our proposed 3-phase model-driven design flow. Moreover, based on this modular and reusable hardware implementation structure as well as the algorithms, we have designed a parametric arbiter generator that automatically generates various multi-facet arbiters. Using this hardware implementation design and the generator, not only a fast and small round-robin arbiter but also other type arbiters were designed and generated on the fly. The hardware implementation algorithms, the generator, and the experiment results all were given to verify their performances. To our knowledge, this is the first time that such a systematic model-driven design approach is proposed in the practical hardware design and such a multi-facet arbiter is designed.

Designing of arbiters has become increasingly important because of their wide use in such as multi-processor system-on-a-chips (MPSoCs) and on- or off- chip high-speed cross-bar switches and networks. In this and an accompanying paper [6], we proposed a new systematic model-driven flow for design of the proposed new scalable multi-facet arbiters through a 3-phase process combined with the template-based modular design approach: the design model derivation phase, the architecture model (or template) design phase as well as arbiter hardware implementation and generation phase. Here, we described the phase 1 of the design flow of how to induce an arbiter design model in detail by careful analysis of arbiter design issues and systematic design space exploring the construction of the model. Then, we continue to discuss the phase 2 of how to derive an architecture model or template using the reusability, modularity and expansibility techniques. With both the design and architecture models, designers can easily design or at least understand and thus choose many kinds of different but better arbiters efficiently. The phase 3 is described in the accompanying paper [6]. To our knowledge, this is the first time that such a systematic model-driven design approach is proposed for the practical hardware design.

As a basic block of a multi-switching-and-processing system, fast and fair arbiters are critical to the efficiency of multi-core computing units, high-speed crossbar switches and routers, which are the key to the performance of on-chip networking/computing in a SoC and NoC. In this paper, a High-Speed and decentralized round-robin arbiter (HDRA) is presented. Unlike the conventional round-robin arbiters, the HDRA design, based on a de-centralized structure, is fast with only O(log4N) in critical path delay, area-efficient, and fair. The design results of it show that the arbitration performance of the HDRA is best compared with all existing arbiters, and still has smaller area cost. This new arbiter is being applied for a patent of the ROC (application No.: 0971xxxxx).