This paper presents an energy-efficient residue amplification for low-power high-speed pipelined SAR ADC, whose residue amplifier is assisted by a dynamic negative capacitance (NC) circuit at the virtual ground. This dynamic NC for the residue amplifier increases the feedback factor while maintaining the closed-loop signal gain, thereby relaxing the requirements of the residue amplifier such as unity-gain bandwidth and open-loop gain, which subsequently leads to a power reduction of the residue amplifier. The proposed dynamic NC addresses the issues associated with static counterparts while maintaining small gain error, increased effective bandwidth, and high energy efficiency. Fabricated in a 28-nm CMOS process, the prototype 11-bit pipelined SAR ADC achieves a signal-to-noise-and-distortion ratio (SNDR) of 58 dB and a spurious-free dynamic range (SFDR) of 77.9 dB with Nyquist input at a sampling rate of 360-MS/s, while consuming only 3.9 mW from a 0.95 V supply. This corresponds to a Walden figure-of-merit (FoM) of 16.7 fJ/conv.-step, making this work competitive among the state-of-the-art ADCs with similar speed and resolution.

This article presents a continuous-time (CT) linear-exponential incremental ADC (IADC) that achieves 15-bit resolution at 250kHz bandwidth with 40 cycles for one conversion. It is based on an energy-efficient CT linear-exponential IADC, which alleviates the requirements of the power-hungry input buffer and loop filter. The proposed IADC employs a coarse 9-bit first-order IADC followed by a fine 8-bit cyclic ADC. The first-order IADC performs the coarse conversion by linearly accumulating input signals, resulting in a small thermal noise penalty. The residual quantization noise is exponentially reduced by the cyclic ADC, significantly shortening the conversion cycle. The cyclic ADC achieves the required accuracy by reconfiguring the loop filter of the coarse IADC and effectively compensating for the excessive loop delay. The prototype CT IADC is fabricated in a 65-nm CMOS process. With a 20MHz clock, it achieves 88.6-dB SNDR, 89.3-dB SNR, 90.1-dB DR, and 103.1-dB SFDR at a conversion rate of 500 kS/s. It consumes only 2.4 mW from a 1.2 V supply. It achieves the Schreier FoM (SNDR) of 168.8dB.

This paper presents a buffer-embedded noise-shaping SAR ADC, whose input buffer separates the capacitive DAC (CDAC) and the sampling capacitor (CS) at the input and output of the input buffer. This compensates for the non-linearity of the input buffer and reduces the CSvalue, resulting in a significant power saving in the input buffer. This buffer-embedded architecture enables the effective implementation of the following passive loop filter and enhances energy efficiency. A bootstrapping switch in the feedback CDAC is coupled to the output of the buffer, thereby avoiding a signal dependency due to the parasitic capacitance of the switch. The buffer-embedded noise-shaping SAR ADC occupies 0.08mm2in a 65 nm CMOS process and features a parasitic input capacitor of 0.2 pF. It achieves 73.8 dB SNDR, 77 dB DR and 87.3 dB SFDR in a 2 MHz bandwidth without any calibration. Including the power consumption of the input buffer, the ADC consumes only 2.1 mW.

This paper presents design considerations for compensation circuitry that addresses OLED display degradation. It focuses on an external compensation method that utilizes an analog-to-digital converter (ADC) in the column driver IC. External compensation has the advantage of addressing both threshold voltage (VTH) and mobility (μ) shifts in the driving thin-film transistor (TFT). By maintaining pixel-to-pixel luminance uniformity, it addresses not only image sticking issues but also leads to a lifetime extension of the OLED pixels. Especially for large-sized OLED panels, it is important to understand the noise contributions from the analog front-end of the compensation circuitry. Noise contributions for each component are thus analyzed for maximizing the overall compensation performance. The analysis results show that the noise from the driving TFT and the display panel's parasitics dominate the total noise and that reducing the noise bandwidth can be an effective noise mitigation strategy. Furthermore, the presented results provide guidance on the required ADC specifications.

Modeling linear periodically time-varying (LPTV) circuits is challenging due to the presence of frequency translation. Many approaches have been proposed that simplify the analysis and provide intuition into the operation of these circuits. It is critical to select the proper model when designing LPTV systems: too complex, and intuition is lost; too simple, and numerical accuracy degrades. This work shows how a conversion matrix-based model can be used for mixer-first receivers with complex feedback in the presence of finite switch transitions. This model accurately predicts S11below -10 dB for all tested transition times, in contrast with prior models, which are shown to be invalid with transitions beyond 2% of the clock period. As a design tool, this approach models gain, harmonic rejection ratio, and noise figure within 0.1 dB of simulation with switch transitions even at 5% of the clock period.

This paper presents a 6.9mW 120fps 28×50 channels capacitive touch sensor for 1mm-φ stylus. A current conveyor analog front-end enables a current signaling before its voltage conversion. A current-driven ΔΣ ADC directly interfaces to the differential current for the digital conversion. A test IC is fabricated in 0.18μm CMOS process. This work achieves SNR of 41.7dB with 1mm-φ stylus, consuming only 6.9mW. This results in an energy efficiency of 0.41nJ/step which is more than 4× improvement on the state-of-the-art works.

A micropower audio delta-sigma modulator is presented for mobile applications. The modulator employs dynamic bias inverter based integrators, which maximizes both gm/IDratio and slew rate while compensating PVT variations. A prototype modulator implemented in a 0.18pm CMOS process features a single-bit third-order topology. The modulator achieves 97.7dB SNDR, 98.6dB SNR, 100.5dB DR, and 105.8dB SFDR in a 20kHz audio band, while consuming only 300pW from a 1.8V supply. This corresponds to a state-of-the-art FoM of 178.7dB.

This paper introduces a 1.35 m long differential capacitive force sensor with a small form factor for a catheter integration. The differential force sensor is realized with two polydimethylsiloxane (PDMS) layers having two different rigidity inserted between flexible printed circuit board (FPCB) electrodes. To achieve the higher precision, we also propose the differential driving method which allows the higher driving voltage even in a low supply system, resulting in the higher SNR. By using the driving voltage of 18 Vp-p under 2 V supply system, the proposed sensor interface has accomplished SNR of 58.22 dB at 100 gf and the force error has reduced from 0.24 gf to 0.18 gf with the equivalent capacitance resolution of 22.2 aF. This work has achieved the state-of-art force resolution by using both the differential driving and CPcancellation technique with a miniature sensor. The proposed sensor can be used for a real time contact force measurement during a catheter ablation or the stiffness detection.

A human eye has the logarithmic response over wide range of light intensity. Although the gain can be set high to identify details in darker area on the image, this results in saturation in brighter area. The gamma correction is essential to fit the human eye. However, the digital gamma correction degrades image quality especially for darker area on the image due to the limited ADC resolution and the dynamic range. This paper proposes a CMOS image sensor (CIS) with nonlinear analog-to-digital converter (ADC) which performs analog gamma correction. The CIS with the proposed nonlinear ADC conversion scheme was fabricated with a 0.35-/spl mu/m CMOS process. The test results show the improved image quality than digital gamma correction.