System-level power analysis is commonly used in modern SoC design processes to evaluate power consumption at early design phases. With the increasing variations in manufacturing, the statistical characteristics of parameters are also incorporated in the state-of-the-art methods. However, the spatial correlation between modules still remains as a challenge for system-level statistical power analysis where power models generated from individual modules are used for analysis efficiency or IP protection. In this paper, we propose a novel method to extract variation-aware and correlation-inclusive leakage power models for fast and accurate system-level analysis. For each individual module we generate a power model with different correlation information specified by the module vendor or customer. The local random variables in the power models are replaced by the corresponding ones at system level to reconstruct the correlation between modules so that the accuracy of system-level analysis is guaranteed. Experimental results show that our method are very accurate while being 1000X faster than Monte Carlo simulation and 70X-100X faster than the flattened full chip statistical leakage analysis.

Performance optimization has become one of the most important problems at all design stages of today's highly integrated circuits. During logic synthesis performance optimization is guided by only rough net delay models. Therefore, net delays cannot be optimized effectively during logic synthesis. As device dimensions are shrinking in deep submicron designs, net delays tend to dominate performance. Consequently, the netlist generated during logic synthesis is suboptimal as only rough approximations for the most dominant part of the path delays are available. In this paper, we present a placement approach that exploits the optimization potential of netlist transformations during placement. As netlist transformations are integrated into the placement process, they can be guided by more accurate net delay models. In contrast to previous approaches that apply netlist transformations during placement, our approach is not restricted to local transformations like buffer insertion and gate resizing, but exploits global dependencies between the signals in a circuit. On the average, the maximum path delay is reduced by 11% compared to the initial performance-driven placement of the original netlist. Furthermore, the experiments show that applying the same netlist transformation procedure before placement yields no improvement as net delays cannot be considered due to missing layout information.

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In this paper, we present a new approach that performs timing driven placement for standard cell circuits in interaction with netlist transformations.As netlist transformations are integrated into the placement process, an accurate net delay model is available.This model provides the basis for effective netlist transformations.In contrast to previous approaches that apply netlist transformations during placement, we are not restricted to local transformations like fanout buffering or gate resizing.Instead, we exploit global dependencies between the signals in the circuit.Results for benchmark circuits show excellent placement quality.The maximum path delay is reduced up to 33 % compared to the initial timing driven placement of the original netlist and up to 18 % compared to the results obtained by consecutive optimization of the netlist and timing driven placement of the optimized netlist.This delay reduction is achieved with almost no increase in chip area. 1.

Article Free Access Share on Reducing power dissipation after technology mapping by structural transformations Authors: Bernhard Rohfleisch Institute of Electronic Design Automation, Technical University of Munich, 80290 Munich, Germany Institute of Electronic Design Automation, Technical University of Munich, 80290 Munich, GermanyView Profile , Alfred Kölbl Institute of Electronic Design Automation, Technical University of Munich, 80290 Munich, Germany Institute of Electronic Design Automation, Technical University of Munich, 80290 Munich, GermanyView Profile , Bernd Wurth Synopsys, Inc., 700 E. Middlefield Rd., Mountain View, CA Synopsys, Inc., 700 E. Middlefield Rd., Mountain View, CAView Profile Authors Info & Claims DAC '96: Proceedings of the 33rd annual Design Automation ConferenceJune 1996 Pages 789–794https://doi.org/10.1145/240518.240667Published:01 June 1996Publication History 25citation233DownloadsMetricsTotal Citations25Total Downloads233Last 12 Months19Last 6 weeks5 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteeReaderPDF

In this paper, we present a novel method for topological delay optimization of combinational circuits.Unlike most previous techniques, optimization is performed after technology mapping.Therefore, exact gate delay information is known during optimization.Our method p erforms incremental network transformations, speci cally substitutions of gate input or output signals by new gates.We present new theory which relates incremental network transformations to combinations of global clauses, and show how to detect such valid clause combinations.Employing techniques which originated in the test area, our method i s c apable to globally optimize large circuits.Comprehensive experimental results show that our method reduces the delay of large standard c ell netlists by 23% on average.In contrast to most other delay optimization techniques, area r e ductions are achieved c oncurrently.