Linear Feedback Shift Registers (LFSRs) have been extensively used for compressed manufacturing test. They have been recently employed as a foundation for porting constrained-random stimuli from a pre-silicon verification environment to in-system validation. This work advances this concept by improving both the hardware efficiency and the duration of in-system validation experiments.

When generating the verification stimuli in a pre-silicon environment, the primary objectives are to reduce the simulation time and the pattern count for achieving the target coverage goals. In a hardware environment, because an increase in the number of stimuli is inherently compensated by the advantage of real-time execution, the objective augments to considering hardware complexity when designing in-system stimuli generators that must operate according to user-programmable constraints. In this paper we introduce a structured methodology for porting in-system the constrained-random stimuli generation aspect from a pre-silicon verification environment.

On-chip trigger units are employed for detecting events of interest during post-silicon validation and debugging. Their implementation constrains the trigger conditions that can be programmed at runtime. It is often the case that some trigger events of interest, which were not accounted for during design time, cannot be detected due to the constraints imposed by the hardware implementation of the trigger units. To address this issue, we present architectural features that can be included into the trigger units and discuss the algorithmic approach for automatically mapping trigger conditions onto the trigger units.

In multi-core designs, distributed embedded logic analyzers with multiple trigger units and trace buffers with real-time offload capability through high-speed trace ports can be placed on-chip. This brings new challenges on how to connect the debug units together in such way that the limited storage space in the trace buffers can be used efficiently. This problem is further aggravated when shadow registers are used to capture data for some signals in the design. In this paper, we propose a new architecture that can dynamically allocate the trace buffers at runtime based on the needs for debug data acquisition coming from multiple data sources and user-programmable priorities. Experimental results show that using the proposed architecture, real-time observability can be improved using only a small amount of on-chip logic hardware, while avoiding excessive storage on-chip.

Scan is a known design-for-test technique in manufacturing test that has been successfully applied also to aid post-silicon debugging on testers. However, to achieve real-time observability in-field, embedded trace buffers are needed. In this paper, we discuss how in the presence of enhanced scan chains, trace buffers can be utilized efficiently for real-time debug data acquisition in-field.

Pre-silicon verification has been traditionally used for eliminating design bugs before tape-out. However, due to the increasing design complexity and the limited accuracy in circuit modelling, the number of the design errors that escape to silicon continues to grow. This is aggravated by the interactions between multiple clock and power domains in the modern system-on-a-chip devices. As a result, structured methods for post-silicon debugging, which aim to detect and localize the bug escapes in silicon, have gained increasing attention in recent years. However, the existing approaches to aid post-silicon debugging primarily rely on the analysis performed using gate-level circuit descriptions. Since design entry is commonly done at the register transfer-level (RTL), the RTL information can be leveraged for the design of the on-chip debug hardware. In particular, in this paper we investigate how to automatically decide which signals to trace in real-time using the RTL information.

The decisions on when to acquire debug data during post-silicon validation are determined by trigger events that are programmed into on-chip trigger units. In this paper, we investigate how to design trigger units that are both resource-efficient and runtime programmable. To achieve these two goals, we introduce new architectural features, as well as an algorithm for automatically mapping trigger events onto trigger units.

To locate and correct design errors that escape pre-silicon verification, silicon debug has become a necessary step in the implementation flow of digital integrated circuits. Embedded logic analysis, which employs on-chip storage units to acquire data in real time from the internal signals of the circuit-under-debug, has emerged as a powerful technique for improving observability during in-system debug. However, as the amount of data that can be acquired is limited by the on-chip storage capacity, the decision on which signals to sample is essential when it is not knownaprioriwhere the bugs will occur. In this paper, we present accelerated algorithms for restoring circuit state elements from the traces collected during a debug session, by exploiting bitwise parallelism. We also introduce new metrics that guide the automated selection of trace signals, which can enhance the real-time observability during in-system debug.

Embedded logic analysis has emerged as a powerful technique for identifying functional bugs during post-silicon validation, as it enables at-speed acquisition of data from the circuit nodes in real-time. Nonetheless, the amount of data that is observed is limited by the capacity of the on-chip trace buffers. This paper introduces an automated method for improving the utilization of the on-chip storage, by identifying a small set of trace signals from which a large number of states can be restored using a compute-efficient algorithm. This enlarged set of data can then be used to aid the search of functional bugs in the fabricated circuit.

When searching for functional bugs in silicon, debug data is acquired after a trigger event occurs. A trigger event can be configured at run-time using a set of control registers that uniquely identify the event that initiates data acquisition. Nonetheless the values loaded in these programmable registers interact only with a set of pre-defined trigger signals that are selected at design-time. If the state conditions required for triggering cannot be expressed directly in terms of the pre-defined trigger signals, the common practice is that the designer manually searches for an equivalent trigger event that can be programmed on-chip. In this paper we investigate if trigger events can be automatically generated from a set of state conditions.

Post-silicon validation is used to identify design errors in silicon. Its main limitation is real-time observability of the circuit's internal nodes. In this paper, we introduce a novel design-for-debug architecture which automatically allocates distributed trace buffers to handle debug data acquisition requests from multiple sources located in different cores. Using resource-efficient and intelligent control placed on-chip, we show how real-time observability can be improved, thus helping bridge the gap between pre-silicon verification and post-silicon validation for SOC designs.

Scan chain division has been successfully used to control shift power by enabling mutually exclusive flip-flops at different times during the scan cycle. However, to control capture power without losing transition fault coverage during at-speed scan test, the existing automatic test pattern generation (ATPG) flows need to be modified. In this paper, we present a novel scan chain division algorithm that analyzes the signal dependencies and creates the circuit partitions such that both shift and capture power can be reduced when using the existing ATPG flows. This novel algorithm has been designed for the broadside test application strategy, and a technique for employing partial scan when dividing the scan chains is also proposed.

This paper discusses an automated method to build scan chains at the register-transfer level (RTL) for power-constrained at-speed testing. By analyzing a circuit at the RTL, where design complexity is lower than at the gate netlist level, one can divide a circuit into multiple partitions, which can be tested independently in order to reduce test power. Despite activating one partition at a time, we show how through conscious construction of scan chains, high transition fault coverage can be achieved, while reducing test time of the circuit when employing third party test generation tools. Furthermore, as shown in experimental results, by constructing scan chains for the partitioned circuit at the RTL, area and performance penalty of the design-for-test hardware may be reduced.

This paper discusses the potential benefits of inserting scan chains (SCs) in hierarchical designs at the register-transfer level (RTL) of design abstraction. Using new algorithms for functional scan chain design, it is shown how tight timing constraints for design-for-test (DFT) planning at RTL can improve the performance of a circuit, when compared to its gate level counterpart, without any loss in testability.

This paper introduces a new method to construct functional scan chains at the register-transfer level aimed at increasing the delay fault coverage when using the skewed-load test application strategy. It is shown how by consciously creating scan paths prior to logic synthesis, both the transition delay fault coverage and circuit speed can be improved.

This paper shows that by creating functional scan chains at the register-transfer level (RTL), not only the timing of the circuit can be improved, but also the test data compression provided from the Illinois scan architecture is similar or even better than the gate level counterpart. It was found that DFT infrastructure built using only the control and data flow information available at the RTL can lead to similar improvements in test data compression (for a fault coverage target over 99%), regardless of the final implementation of the logic network or the manufacturing test set.