The identification of the multiple model-based Hammerstein parameter varying systems is studied in this paper. The parameters of the considered systems vary as the systems perform on different operating conditions. For each local model, the input nonlinear output-error structure is introduced to describe the dynamical property. Allocating an exponential weighting function to each local model, the nonlinear dynamics of the global system is approximated by combining all local models. The variational Bayesian (VB) approach is adopted to find the solution to the problem of parameter estimation. For the parameter uncertainties, instead of the point estimation, the posterior distribution of each model parameters is obtained under the framework of the VB approach. Two numerical simulation examples and an experiment carried on a multitank system have been employed to demonstrate that the proposed approach can work effectively.

Due to high switching activities in test mode, circuit power consumption is higher than its functional operation. Large switching in the circuit during launch-to-capture cycles not only negatively impacts circuit performance causing overkill, but could also burn tester probes during wafer test due to the excessive current they must drive. It is necessary to develop a quick and effective method for evaluating each pattern, identifing high-power patterns considering functional and tester probes' current limits and making the final pattern set power-safe. Compared with previous low-power methods that deal with scan structure modification or pattern filling techniques, the new proposed method takes into account layout information and resistance in the power distribution network and can identify peak current among C4 power bumps. Post-processing steps replace power-unsafe patterns with low-power ones. The final pattern set provides considerable peak current reduction while fault coverage is maintained.

Researchers, based primarily on theoretical analysis of different coverage metric, have proposed the need to cover small delay defect (SDD). There is very little silicon data justifying the need to add SDD tests to the manufacturing flow. This paper attempts to fill this gap. A high volume manufacturing experiment to ascertain the added screening capability of defective parts and infant mortality of FAST_TDF tests are described. Quantitative silicon data are presented.

Existing commercial power sign-off tools analyze the functional mode of operation for a small time window. The detailed analysis used makes such tools impractical in determining test peak power where a large amount of scan shift cycles have to be analyzed. This paper proposes an approximate test peak power analysis flow capable of computing test peak power at each power bump in the design. The flow uses physical design information, like power grid, power bump location, packaging information, along with the design netlist. We present correlation studies, on industrial design, and show the proposed flow to correlate within 5%of the accurate commercial power sign-off tool. In addition, we demonstrate that this flow, unlike the commercial power sign-off tool, can process a very large number of transition delay tests in a reasonable time.

As technology feature geometries shrink, failures caused by signal integrity issues have become prominent during test. To avoid the time consuming silicon inspection and reduce the engineering cost and effort for failure analysis, a fast and cost-effective diagnostic flow is proposed in this paper. The flow targets delay faults and can be used to (1) identify noise-related failures with a quiet pattern and (2) evaluate the failed pattern in terms of its noise-induced delay to help identify the root cause of failure. A novel procedure is developed to generate a quiet pattern to help differentiate sources of the failure. The quiet pattern targets the same physical defects as the failed pattern but offers much lower noises level. A pattern evaluation procedure is used to evaluate the noise-induced delay. The proposed procedures are implemented on ITC'99 b19 benchmark. Simulation results demonstrate the effectiveness of the proposed procedure in identifying the failure mechanism. The noise-induced path delay for both failed patterns and diagnostic quiet patterns are thoroughly evaluated.

As technology shrinks, gate sensitivity to noise increases due to supply voltage scaling and limited scaling of the voltage threshold. As a result, power supply noise (PSN) plays a greater role in sub-100 nm technologies and creates signal integrity issues. It is vital to consider supply voltage noise effects: 1) during design validation to apply sufficient guardbands to critical paths, and 2) during path delay test to ensure the performance and reliability of the chip. In this paper, a novel layout-aware pattern generation procedure is proposed to maximize PSN effects on critical paths considering the impact of local voltage drop. The proposed pattern generation and validation flow is implemented on the ITC'99 b19 benchmark. Experimental results for both wire-bond and flip-chip packaging styles are presented. Results demonstrate that our proposed method is fast, significantly increases switching around the functionally testable critical paths, and induces large voltage drop on cells placed on the critical paths which results in increased path delay. The proposed method eliminates the very time consuming pattern validation phase that is practised in industry.

Large switching during launch-to-capture cycle in delay test not only negatively impacts circuit performance causing overkill, but could also burn tester probes due to the excessive current they must drive. It is necessary to develop a quick and effective method to evaluate each pattern, identify high-power ones considering functional and tester probes' current limit and make the final pattern set power-safe. Compared with previous low-power methods that deal with scan structure modification or pattern filling techniques, the new proposed method takes into account layout information and resistance in power distribution network and can identify peak current among C4 power bumps. Post-processing steps replace power-unsafe patterns with low-power ones. The final pattern set provides considerable peak current reduction while fault coverage is maintained.

At-speed scan testing has become mandatory due to the extreme CMOS technology scaling. The two main at-speed scan testing schemes are namely Launch-Off-Shift (LOS) and Launch-Off-Capture (LOC). As it can be easily implemented, LOC has been widely investigated in the literature in the last few years, especially regarding test power consumption. Conversely, LOS has received much less attention. In this paper, we propose a comparison between the two testing schemes in terms of transition fault coverage and power consumption, in order to quantify the pros and cons of LOS with respect to LOC. This study shows that LOS not only exhibits higher performance in coverage but also does not require as much extra power as predicted, especially in terms of peak power. These facts may represent convincing arguments for its wider use and development.

International audience

Production-oriented virtual enterprise is a more important form in the virtual enterprise, quality information management plays an irreplaceable role in production-oriented virtual enterprise. According to life-cycle theory of the virtual enterprise and the condition of information technology, combing with quality assurance model and started with customer relations, quality information management system of production-oriented virtual enterprise was built. It is conducive to identify, acquire and deal with quality information, in order to provide quality information management guarantee for production-oriented virtual enterprise.

As technology scales, gate sensitivity to noise increases due to supply voltage scaling and limited scaling of the voltage threshold. As a result, power supply noise plays a greater role in sub-100nm technologies and creates signal integrity issues in the chip. It is vital to consider supply voltage noise effects (i) during design validation to apply sufficient guardbands to critical paths and (ii) during path delay test to ensure the performance and reliability of the chip. In this paper, a novel layout-aware pattern generation procedure for maximizing power supply noise effects on critical paths while considering local voltage drop impacts is proposed. The proposed pattern generation and validation flow is implemented on the ITC’99 b19 benchmark. Experimental results for both wire-bond and flip-chip packaging styles are presented in this paper. Results demonstrate that our proposed method is fast, significantly increases switching around the functionally testable critical paths, and induces large voltage drop on cells placed in the critical paths which results in increased path delay. The proposed method eliminates the very time consuming pattern validation phase that is practiced in industry.

Power distribution networks (PDNs) have been a vital part of modern designs. However, scaling technologies have increased the likelihood of defects in the PDN that may affect yield, escape, and reliability. Failure analysis is particularly difficult since there is no direct access to the PDN as there is to the design logic. We present a flow that generates transition-delay fault patterns to target open defects on the PDN. The flow identifies regions that could be susceptible to open defects and generates patterns that will exercise those regions to increase the likelihood of a timing failure should a defect exist in the PDN.