Demo Data from EDBT 2026 / reviewers in the wild / expert
Conor S. Rafferty
dblp:39/248
· DBLP profile ↗
3ranked-venue papers
1as first author
0since 2021 · last 1988
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 2 · 1 first-authorGraphics, computer vision, multimedia, augmented reality and games · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
2 papers |
Integrated circuit design · 66% Electronic design automation · 17% High-performance computing · 17% |
Topics — the 5 heaviest of 5, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Integrated circuit design
analog and mixed-signal circuits |
0.0 | 1 | 1987 | Analysis of Velocity Saturation and Other Effects on Short-Channel MOS Transistor Capacitances · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1987 |
Integrated circuit design › analog and mixed-signal circuits › device modeling
MOS capacitance model |
0.0 | 1 | 1987 | Analysis of Velocity Saturation and Other Effects on Short-Channel MOS Transistor Capacitances · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1987 |
Integrated circuit design › semiconductor devices
short-channel effects |
0.0 | 1 | 1987 | Analysis of Velocity Saturation and Other Effects on Short-Channel MOS Transistor Capacitances · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1987 |
Electronic design automation › technology computer-aided design
device simulation |
0.0 | 1 | 1985 | Iterative Methods in Semiconductor Device Simulation · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1985 |
High-performance computing › numerical linear algebra › linear solver
iterative linear solvers |
0.0 | 1 | 1985 | Iterative Methods in Semiconductor Device Simulation · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1985 |
Methods — techniques the papers use, named apart from their topics
two-dimensional device simulation · 0.0capacitance extraction · 0.0sparse gaussian elimination · 0.0operator decomposition · 0.0newton method · 0.0incomplete factorization · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1988 | Nonobtuse Triangulation of Polygons
Brenda S. Baker, Eric Grosse, Conor S. Rafferty |
Discret. Comput. Geom. | 3 |
| 1987 | Analysis of Velocity Saturation and Other Effects on Short-Channel MOS Transistor CapacitancesabstractIn order to analyze short-channel effects of MOS transistor ac characteristics, a two-dimensional device simulator has been used to extract MOS transistor capacitances. The results of simulation and measurements agree well. The causes of short-channel effects have been understood and explained by the simulations. Two-dimensional effects and velocity saturation are the main causes of short-channel effects in MOS transistor capacitances. Two-dimensional simulation was found to be a useful tool for studying mobility models, as well as for obtaining capacitance models for circuit simulation. Hiroshi Iwai, Mark R. Pinto, Conor S. Rafferty, J. E. Oristian, Robert W. Dutton |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. | 3 |
| 1985 | Iterative Methods in Semiconductor Device SimulationabstractThis paper examines iterative methods for solving the semiconductor device equations. The emphasis is on fully coupled methods, because of the failure of decoupled methods for on-state devices. Using the PISCES-II device simulator as a vehicle, incomplete factorization and operator decomposition iterative methods are presented for solving the Newton equations. The dependencies of these methods on factors such as choice of variables, bias condition and initial guess are analyzed. The results are compared with sparse Gaussian elimination. Conor S. Rafferty, Mark R. Pinto, Robert W. Dutton |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. | 1 |