This paper presents a 64-state, ½-rate asynchronous Viterbi decoder suitable for wireless and mobile applications. The decoder uses a novel dynamic Current Sensing Completion Detection (CSCD) technique and achieves significant power reduction while maintaining speed. The decoder, implemented in a 90 nm CMOS technology, occupies an area of 0.81 mm2 and operates at 378 Mb/s while consuming 45 mW: a 43% power delay product improvement when compared to its synchronous counterpart.

This paper describes the implementation of an asynchronous 64-state, 1/2-rate Viterbi decoder using an original architecture and design methodology. The decoder is intended for wireless communications applications, where bit rates over 100 Mb/s and minimum power consumption are sought. The choice of an asynchronous design was predicated by the power and speed advantages of such a methodology. Asynchronous designs are inherently data driven and are active only when doing useful work, enabling considerable savings in power and operating at the average speed of all components. The decoder, implemented in a 0.18 µm CMOS technology, occupies an area of 2 mm 2 and operates above 200 Mb/s while consuming 85 mW: a 55% power reduction when compared to state of the art synchronous design implemented in a 0.25 µm technology.

A novel phase shifted (PS) wireless transmitter architecture is presented. The PS transmitter employs switching power amplifiers, operates without mixers and provides an intermodulation distortion-free output spectrum, making it a suitable choice for mobile communication systems. The RF blocks of the PS transmitter include a local oscillator, phase shifters, switching class F power amplifiers and wideband output combiners. The PS transmitter, implemented in a standard 0.18 /spl mu/m CMOS technology, occupies an area of 5 mm/sup 2/. It operates from a 1 V supply and provides 40 dBc adjacent channel power ratio for output bandwidths up to 50 MHz at 8 GHz. The combined class F PAs in the PS transmitter provide 20 dBm output power with a 38% power added efficiency.

Article 1 V, 1.9 GHz mixer using a lateral bipolar transistor in CMOS Share on Authors: Song Ye University of Toronto, 10 King's College Road, Toronto, Ontario, M5S 3G4, Canada University of Toronto, 10 King's College Road, Toronto, Ontario, M5S 3G4, CanadaView Profile , Koji Yano Yamanashi University, Takeda-4, Kofu, Yamanashi 400-8511, Japan Yamanashi University, Takeda-4, Kofu, Yamanashi 400-8511, JapanView Profile , C. Andre Salama University of Toronto, 10 King's College Road, Toronto, Ontario, M5S 3G4, Canada University of Toronto, 10 King's College Road, Toronto, Ontario, M5S 3G4, CanadaView Profile Authors Info & Claims ISLPED '01: Proceedings of the 2001 international symposium on Low power electronics and designAugust 2001 Pages 112–116https://doi.org/10.1145/383082.383106Online:06 August 2001Publication History 3citation223DownloadsMetricsTotal Citations3Total Downloads223Last 12 Months1Last 6 weeks1 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteGet Access

A pipelined 15/spl times/15 bit multiply-accumulate (MAC) unit, optimized for energy recovery systems, is presented. The applied architectural and circuit level optimizations are aimed at minimizing the total non-recoverable energy per computation. For that purpose, the number of pipeline stages is minimized, utilizing logic gates based on high fan-in differential NMOS trees. The MAC includes three pipeline stages operated from a two-phase non-overlapping power clock and processes one multiply-accumulate operation per clock cycle. Implemented in 0.25 /spl mu/m CMOS process and powered from a 1 V power supply, this circuit uses 4.5 pJ of recoverable energy per clock cycle, while dissipating 0.28 pJ of non-recoverable energy.

Registers and datapath multiplexers exist in most DSP datapaths. Although not performing computations, they are necessary for the dataflow control and they consume energy. This paper describes the nature of register and multiplexer energy consumption in modern low power CMOS processes, shows its strong dependence on architectural and layout design and provides practical design guidelines for micropower implementation.

A low-power (2.5 V) current-mode analog to digital converter suitable for mobile radio transceiver application is presented. It uses current injection technique to increase the speed of current mirrors. The 4-bit ADC is implemented in 1.2 /spl mu/m CMOS technology. It has a conversion rate of 4.5 MHz, a power dissipation of 0.5 mW and an active chip area of 0.02 mm/sup 2/.>

An imager with built-in image-velocity computation capability is described. The image-velocity computation technique is based on signals propagating on delay lines. Silicon implementation using 3- mu m-CMOS technology is described. Experimental results show that a computational error of less than 20% can be achieved using available fabrication technology. This figure can be reduced by using larger arrays and better implementations of delay gates.>

A technique for image-velocity computation is described. Using one set of intersecting delay lines that are physically perpendicular to each other, the two perpendicular components of image velocity can be computed separately if the image area is known. To compute the image velocity without knowledge of the image area, two sets of intersecting delay lines are required. This technique is suitable for analog VLSI implementation.>

Unrealistic parameter values and poor experimental agreement are two problems often encountered using the MOS3 model in SPICE2. The source of the discrepancy is attributed to MOS3's simplified treatment of the mobility degradation phenomenon, which generally results in an artifically exaggerated value for the carrier velocity. Practically, this discrepancy can be eliminated by introducing a new empirical factor (DEL) into the mobility model, thereby permitting SPICE users to accurately simulate both triode and saturation regions of p- and n-channel transistors. DEL is determined using an extraction algorithm which systematically extracts MOS3 parameters and characterizes the extent of mobility degradation in the transistor's triode region.