This paper proposed a modified two-stage cascaded hybrid buck converter with reduced conduction loss, and simplified interleaving PWM circuit. The proposed converter reduces the conduction loss with fewer total switches and high-voltage switches. Also, the proposed converter achieves the inherent self-balanced flying capacitor voltages. Besides, the proposed converter simplifies the interleaving PWM circuit with the single ramp signal by digital logic. Moreover, the proposed converter avoids extra supply to feed the drivers. Simulated with a 130-nm BCD technology, the proposed converter regulates a 0.4 V - 1.2 V output from a 5 V input voltage, and it achieves the high peak and 1A-heavy-load efficiencies of 96% and 92.5%, respectively.

This paper proposes a modified interleaving resonant switched capacitor converter with reduced output resistance and in-situ startup. The operation principle, especially the average output voltage, the average flying capacitor voltages and the output resistance are theoretically deduced. The proposed converter reduces the output resistance by using less switches in some current paths. Besides, the proposed converter takes an in-situ flying capacitor pre-charge scheme to guarantee a safe startup. Here, we simulate both the conventional and the proposed converters in Cadence Spectre with the commercial device models. The proposed converter improves the heavy-load efficiency from 92.7% to 93.2% with$\mathrm{V}_{\text{IN}} = 48\ \mathrm{V}$and$\mathrm{V}_{\text{OUT}} = 12\ \mathrm{V}$, leading to around 7% total loss reduction.

Parallel connected low-dropout regulators (LDOs) are commonly used to share the large load current in communication baseband systems. This paper presents a PCB-friendly, reconfigurable master-slave parallel LDO scheme with analog regulation and digital distribution, to deliver Ampere-level load current with small current mismatches. The proposed LDO adopts a series analog-digital merged control, where the first loop is a high-gain analog error amplifier for high-accuracy regulation, and the second loop utilizes a 6-bit successive approximation register (SAR) analog-to-digital converter (ADC) for the tradeoffs between resolution, energy-efficiency, and fast response. Each LDO can be configured into the master or slave mode. When multiple LDOs are connected in parallel, the master LDO also controls the digital power cells in the slave LDOs. By employing an auxiliary constant current control, the power cells in each LDOs work as a constant current source array. The same control code naturally enables the output current balancing among each LDOs. Fabricated in 65-nm CMOS, the proposed LDO obtains an excellent load regulation of < 1.5mV/A across the full load range of 0-1A, with 99.9% peak current efficiency. For four parallel LDOs with each delivering 1-A load current, the measured current-sharing mismatch is only < 0.76% with no additional external components.

This paper proposes a hybrid boost converter for $\gt100V$ LED lighting applications. The proposed boost converter uses one flying capacitor to reduce the switch voltage stress, average inductor current, and inductor current ripple, and also to prolong the duty cycle (D) for the same voltage conversion ratio (M). Therefore, the proposed topology has reduced switching, conduction, and core losses, exhibiting also an enhanced step-up capability. Hence, the proposed boost converter considerably improves the power conversion efficiency (PCE), with M=(2–D)/(1–D). Besides, the proposed boost converter automatically sets the voltage on the flying capacitor to VOUT– $\mathrm{V}_{IN}$. Here, we simulate both the conventional and the proposed boost converters in Cadence Spectre with commercial device models. The proposed boost converter improves the peak PCE from 96.8% to 97.4%, with ${V}_{IN}=24V, V_{OUT} =103.5V$, and IOUT=1 A. That is equivalent to 18.75% total loss reduction.

This paper presents a dual-branch series-parallel hybrid buck converter with flying capacitor voltage auto-balancing and reduced output impedance. The proposed converter automatically and inherently balances the flying capacitor voltages as one-third of the input voltage. Besides, the proposed converter operates in four states per cycle rather than the conventional six states, leading to a feasible Type-III compensation of the analog pulse-width modulation (PWM) controller. Moreover, due to the multiple parallel current paths in the switched-capacitor network, the proposed converter reduces the output impedance, thus decreasing the conduction loss. Finally, validated in 65-nm CMOS, the proposed converter regulates a 0.55 V–1 V output voltage from a 3.6 V input voltage over a large output power of 0.45 W with 82% peak efficiency, and switching frequency up to 5 MHz. It also automatically sets the flying capacitor voltages at 1.2 V.

This paper presents a single-stage tri-path buck converter with reduced inductor current and self-balanced flying capacitor voltage. The proposed converter introduces capacitor paths to reduce the average inductor current and inductor current ripple, hence decreasing the conduction loss. Operating with two states per conversion cycle, it exhibits a relatively low voltage conversion ratio of${D}$/(1$+\,\,2{D}$). Besides, it realizes a self-balanced flying capacitor voltage in the charge redistribution phase. Similar to the conventional buck converter, the proposed converter in continuous-current mode only has two complex poles. Therefore, we design a Type-III compensator to obtain a good transient response. Moreover, the circuit does not require extra supplies for gate drivers due to the reutilization of the flying capacitor voltages, eliminating additional circuit and power overheads. The proposed converter, validated in a 65-nm standard CMOS technology, regulates a 0.7 V – 1 V output voltage from a 3.3 V – 4 V input voltage, delivering a maximum output power of 270 mW. The peak efficiency is 84%, with a switching frequency up to 5 MHz.

Since the power consumption of data centers keeps increasing, a 48-V rack power distribution system replaces the conventional 12-V power bus to reduce the power delivery IR losses. Meanwhile, the 48 V needs conversion into 1 V or lower at the point-of-load for microprocessors. A 48V-to-12V DC-DC converter can serve as a first stage between the huge gap of 48V-to-1V, in a two-stage voltage regulator module (VRM). Thus, this paper presents a 3-phase resonant switched-capacitor ( 3Φ-ReSC) converter as the first stage of the VRM. Different from the reported solutions, 3-phase resonant operation reduces the current stress across each small-size GaN switch, and thus improves the power conversion efficiency. In addition, we also present the theoretical analysis and design procedures for the 3Φ-ReSC converter. We demonstrated the proposed 3Φ-ReSC converter with a 98% peak power efficiency at an output current of about 1 A, with a maximum output current of 10 A.

The modular multilevel converter with series and parallel connectivity was shown to provide advantages in several industrial applications. Its reliability largely depends on the absence of failures in the power semiconductors. We propose and analyze a fault-diagnosis technique to identify shorted switches based on features generated through wavelet transform of the converter output and subsequent classification in support vector machines. The multi-class support vector machine is trained with multiple recordings of the output of each fault condition as well as the converter under normal operation. Simulation results reveal that the proposed method has high classification latency and high robustness. Except for the monitoring of the output, which is required for the converter control in any case, this method does not require additional module sensors.