A heuristic routing approach for generating transistor schematic diagrams is presented. The method consists of two steps: global routing and channel routing. The global routing step partitions and routes the interconnections, into three levels of abstraction with domain knowledge. It forms desirable intra-block routing styles and local connection patterns, and achieves a reduction of net bends and lengths. Channel routing minimizes net crossovers by applying decycling and ordering techniques achieving nonoverlapping routing with a small number of net crossovers.>

A global circuit structure is established from the circuit net-list based on knowledge about CMOS circuits. This approach first partitions the circuit network and then assigns signal flow directions accordingly. The information obtained is absent in the net-list but explicitly present in schematic diagrams. Such interpretation of a circuit network can provide extra heuristics to assist in various CMOS circuit design tasks.

An approach is presented for generating structurally near-optimal logic schematic diagrams from net lists. Unlike previous methods, preprocessing is performed to globally reduce the structural complexity of the anticipated schematic topology before the extraction of structural clusters. Since the optimized circuit topology may still be nonplanar, a novel weighted crossover resolution method is applied to temporarily remove costly local nets to extract important structural clusters and aligned nets in the planarized topology. A grid is assigned so that placement and global routing of the logic schematics can be generated with the desired topology that includes well-formed structural clusters.>

This paper describes a system capable of generating schematic diagrams for gate-level digital logic circuits given only their net-list descriptions in the VHSIC (Very High Speed Integrated Circuit) Hardware Description Language (VHDL). A combination of algorithmic and heuristic methods are employed to synthesize a schematic drawing which is as aesthetically pleasing and functionally readable to human designers as possible. A methodology for generating schematics which contain feedback loops is presented

This paper describes an approach to symbolic transistor placement from a CMOS circuit net-list as part of an automatic custom cell layout system, PLAY. It consists of two parts, extraction and refinement. The extraction process defines a set of patterns using local connection relationships. Refinement procedures assign topological attributes to each transistor through these patterns and relationships along with other heuristic knowledge. This paradigm provides a new way to embed designers' knowledge for circuit layout. Although only CMOS circuit layout placements are demonstrated, this approach can readily be extended to other technologies. Comparison between PLAY and manual design results is also reported.

A hybrid computing technique is presented for improving the resolution of the discrete-space discrete-time (DSDT) resistive network method and the treatment of large scale systems encountered in the solution of partial differential equations.

This crrespondence is concerned with the develop-ment of a simple set of rules used to determine disjunctively decomposable logic functions by means of a single Karnaugh map.