Tetsufumi Tanamoto

dblp:39/3732 · DBLP profile ↗
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2ranked-venue papers
0as first author
0since 2021 · last 2010
0000-0002-1373-2812ORCID · verified

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Reconfigurable computing and FPGAs · 70% Memory systems · 30%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Reconfigurable computing and FPGAs › FPGA implementation
FPGA circuit design
0.112010
High-performance FPGA based on novel DSS-MOSFET and non-volatile configuration memory (abstract only) · FPGA 2010
Reconfigurable computing and FPGAs › FPGA configuration
non-volatile configuration memory
0.112010
High-performance FPGA based on novel DSS-MOSFET and non-volatile configuration memory (abstract only) · FPGA 2010
Memory systems
non-volatile memory
0.112010
High-performance FPGA based on novel DSS-MOSFET and non-volatile configuration memory (abstract only) · FPGA 2010
Reconfigurable computing and FPGAs
FPGA power reduction
0.012010
High-performance FPGA based on novel DSS-MOSFET and non-volatile configuration memory (abstract only) · FPGA 2010

Methods — techniques the papers use, named apart from their topics

physical layout design · 0.1SPICE modeling · 0.1
YearPublicationVenuePosition
2010 High-performance FPGA based on novel DSS-MOSFET and non-volatile configuration memory (abstract only)
abstract
New FPGA deign using Dopant-Segregated Schottky MOSFET (DSS-MOSFET) and nonvolatile configuration memory (NCM) has been presented. Both of these devices can be fabricated by mature process for mass production. DSS-MOSFET has very low On-state resistance due to the high density dopant at source/drain junction. Therefore, FPGA is one of the best applications for the use of DSS-MOSFET since DSS-MOSFET can effectively improve not only CMOS logic performance but also pass-transistor logic performance. In addition, NCM with large On/Off resistance ratio, such as ionic memory, is adopted to replace SRAM-based configuration memory. Since NCM is fabricated between interconnect layers of CMOS, silicon area is smaller than in the case of SRAM. Furthermore, since NCM is a nonvolatile device, it is possible to reduce the power consumption by cutting off the power supply of unused circuit blocks. We developed a SPICE model of DSS-MOSFET to measure the delay of basic circuit in FPGA, and confirmed about 18% delay improvement for look-up-table with four to six inputs. We also designed physical layout to evaluate the area reduction of configuration memory, and verified the area of NCM is about 2.8X smaller than that of SRAM-based. Twenty largest MCNC benchmarks indicate that 26% improvement in critical path delay on average, and 15% improvement in area delay products on average can be achieved by the use of DSS-MOSFET and NCM.
Shinichi Yasuda, Tetsufumi Tanamoto, Kazutaka Ikegami, Atsuhiro Kinoshita, Keiko Abe, Hirotaka Nishino, Shinobu Fujita
FPGA2
2009 Perspectives and Issues in 3D-IC from Designers' Point of View
abstract
Recent progress of through-silicon-via (TSV) process is so impressive that everyone can expect real 3D-IC era. The most valuable advantages of 3D-IC is decreasing interconnects. Although analysis of this advantages has been reported in some specific case study, the general theory for quantitative analysis has not been studied. In some cases, the advantage of 3D-IC has been overestimated and much different from that of real chip designs expected. This paper presents the qualitative analysis of general 3D-IC design especially for sub-65nm CMOS generation from designers' point of view. What is understood from this paper is how important IC-design is for 3D-IC and how to gain a big advantage of 3D-IC.
Shinobu Fujita, Keiko Abe, Kumiko Nomura, Shinichi Yasuda, Tetsufumi Tanamoto
ISCAS5