This work presents a novel concept of self-impedance matching in rectifier design by integrating a driving rectifier in parallel with a conventional voltage doubler circuit. The input impedance of the wideband rectifier is perfectly matched with the use of driving rectifier, which consists of a half-wave rectifier, a series stub line, and a grounding capacitor. The series stub adjusts the operating frequency and the efficiency bandwidth (EBW) of the proposed rectifier. This approach streamlines the rectifier design by eliminating additional input impedance matching networks and offers simultaneous control of EBW and operating bandwidth. Instead of a conventional lossy microstrip line, a Defected Ground Structure (DGS) is employed to design a high-impedance series stub line which makes the proposed circuit compact with improved quality factor. The experimental results highlight the effectiveness of the proposed rectifier, achieving more than 50% power conversion efficiency (PCE) for the frequency range of 3 GHz to 5.8 GHz, covering entire sub-6 GHz band of the 5G network with minimal variation. The fabricated prototype is the most compact design, with a circuit size of only 0.756 cm2.

A K-band two-stage power amplifier (PA) with capacitive-feedbacked cold-phase compensator (cold-PC) linearizer and power-added-efficiency (PAE) enhancer is introduced in 180-nm CMOS technology. This cold-PC consists of two parts. First, a cold-FET analog pre-distorter (APD) with a new capacitive-feedbacked technique is proposed to improve the linear behavior of the PA by enhancing the corresponding APD’s compensation slope. The proposed implementation has a reduced insertion loss and a minimal chip area overhead. Second, a low-pass two-tunable inductive and capacitive PC is proposed to solve the phase shift problem at intermediate nodes that would enhance the PAE of the stacked-transistors configuration. The implemented PA achieves, at 23.5-GHz, a maximum measured PAE of 21.2%, output power at the 1-dB compression point (OP1dB) of 13.4-dBm, and saturated output power of 15-dBm using a total chip area of 0.58 mm2. Employing the proposed cold-PC results in a decrease of the measured error vector magnitude (EVM) of the 400-MHz 5G-NR of 64-QAM modulated signal and an increase of the OP1dB and its PAE by 2.5-dB and 7%, respectively (enhancement by 78% and 72% from the original case, respectively), which, to the best of authors’ knowledge, is the highest reported enhancement of the linearizers of k-band PAs.

This work proposes a new technique to reduce the phase noise (PN) and improve the tuning sensitivity of$K$-band voltage-controlled oscillators (VCOs) by increasing the quality ($Q$-) factor of the switched resonator. The proposed switched resonator consists of a high$Q$-factor half-circle inductor in parallel with an improved switched varactor and operates in four different frequency bands using a single switching voltage pin. The proposed switched resonator introduces one pole before the parallel resonance frequency, which sharpens the skirt characteristics of the scattering parameters of the resonator. The chip is implemented in the 0.18-$\mu \text{m}$CMOS technology, and the proposed VCO operates in four different frequency bands, with a total frequency tuning range (FTR) of 10.7%. The first band ranges from 19.4 to 19.84 GHz, the second band ranges from 19.8 to 20.3 GHz, the third band ranges from 20.25 to 20.73 GHz, and the fourth band ranges from 20.7 to 21.3 GHz. The VCO core circuit draws a dc current of 5 mA from a 1.8-V supply and achieves a PN of −110.7 at 1-MHz offset from a 20.25-GHz carrier. This proposed oscillator achieved a figure of merit (FoM) of −186.8 dBc/Hz, while the FoM taking account of the tuning voltage (FoMT/V) is −181.4 dBc/Hz.

This work proposes a new theory to improve the phase noise of a Voltage-Controlled Oscillator (VCO) by introducing dual series resonances around the parallel resonance of an LC-tank circuit. The overall circuit has an improved susceptance slope parameters, which results in the improvement of quality (Q-) factor. Later, its effectiveness is demonstrated to design a low phase noise K-band VCO. The proposed characteristics are realized by a compact defected ground structure (DGS) resonator in a coplanar strip line (CPS) topology. The DGS is loaded by a capacitor, and this combination introduces the parallel resonance. The CPS signal line is implemented with high characteristic impedance to introduce a series inductance. Then, a gap in the CPS is introduced with a loading series capacitance forming a series resonance circuit with the CPS inductance. The overall combination of the series and parallel resonance circuits allowed the targeted two series resonances before and after the parallel resonance. The design is implemented in 0.18-μm CMOS technology, and the post-layout simulation shows that the VCO has a phase noise of −112.31 dBc/Hz @1 MHz offset of 22.07 GHz oscillation, which is 2.3 dB improvement compared to single series resonance VCO. The VCO consumes 4 mW power resulting in a figure of merit (FoM) of −193.2 dB.

In this paper, a new theory to improve the phase noise of a Voltage-Controlled Oscillator (VCO) utilizing dual series and parallel resonance to improve the susceptance slope parameter of the resonator circuit is proposed, and its effectiveness is demonstrated to design a low phase noise K-band VCO. The proposed dual resonance is realized using a compact defected ground structure (DGS) resonator, which achieve the additional series resonance by loading its transmission line by a series capacitor. The resulting susceptance slope, and active quality (Qk-) factor of the resonator circuit enhance that, in returns, improves the phase noise by 3.2dB of the same circuit without the series resonance. The design is implemented in 0.18 μm CMOS technology, and the post-layout simulation results show that VCO has a tuning range of 3.4%, and low phase noise with − 111.9 dBc/Hz @1 MHz offset at 21.04 GHz oscillation. The VCO consumes 7.5 mW power resulting in a FoM of −188.7 dB.

Compact modeling of phase-locked loop (PLL) frequency synthesizer is proposed to reduce transient phase noise and jitter simulation time. Conventional small-signal noise assumption based frequency-domain simulation approach produces inaccurate results for nonlinear PLLs. Accurate analysis of nonlinear PLL are possible through time-domain, or transient noise simulation but time-domain simulation is computation-intensive and time-consuming. This paper presents a practical solution for transient phase noise and jitter analysis using compact modeling techniques. It features an autoregressive moving average process modeled voltage-controlled oscillator with fractional calculus and wavelet transform for phase noise decomposition and reconstruction, thereby reducing the phase noise and jitter simulation time to 25.8% of the transistor-level simulation with 0.4 dB @ 1 MHz phase noise error and 0.3 ps long-term jitter error for a 2 GHz PLL frequency synthesizer in a 65 nm CMOS process.

A multicode optical code-division multiplexing (OCDM) is proposed to support the dynamic changes in the requested traffic demand in OCDM networks by adapting the number of allocated codes according to the requested transmission rate. In order to support time-variant data rates and multiservice transmissions; a multicode variable-weight 2D one-coincidence frequency hopping code/optical orthogonal code (OCFHC/OOC) is employed as the signature code in the proposed system. Two multicode assignment methods, namely, random multicode assignment (RMA) policy and uniform multicode assignment (UMA) policy, are presented. For each code assignment method, we drive the probability density function (pdf) of the number of active codes in each wavelength group. The bit error probability (BEP), the probability of degradation, and the blocking probability are derived as network performance key parameters. The proposed system has a simplified routing and code assignment process with a lower blocking probability. Our numerical results indicate that the network teletraffic capacity and blocking probability can be improved significantly using UMA policy and call admission control.

Optical code-division multiplexing (OCDM) systems use short pulses compared with bit-duration to achieve high transmission rate. The use of short pulses poses several problems as a result of group velocity dispersion (GVD), intersymbol interference (ISI) (due to avalanche photodiode (APD) buildup time), and receivers limited bandwidth. In this paper, an OCDM system employing code-shift keying (CSK) and overlapping pulse-position modulation (OPPM) signaling is proposed and theoretically investigated. By using CSK while maintaining same data rate, the chip duration can be increased to counteract the GVD effect in 2D OCDM systems. Moreover, by increasing the chip duration, the chip rate is decreased and the stringent requirement on receiver bandwidth is relaxed. In addition, using overlapping property in OPPM allows for further chip duration increase. We consider using correlation receivers with hard-limiters and APDs at the receiver side. The bit error probability (BEP) of the proposed system is derived taking into account the impacts of APD noise, thermal noise, GVD, ISI, and multiple-access interference (MAI). A performance comparison between OOK-, PPM-, OPPM-OCDM and the proposed system is carried out. Our results reveal that the use of CSK/OPPM-OCDM with data rate constraint allows the reduction of MAI, GVD and ISI effects with improved spectral efficiency.

Compact model extraction of phase-locked loop (PLL) frequency synthesizer using system identification techniques is proposed to reduce post-layout simulation time. This is the first published compact model for PLL using system identification techniques. It features an autoregressive exogenous model for the charge pump and the loop filter with a lookup table for nonlinearity compensation and a radial basis function neural network for the voltage-controlled oscillator with nonlinear frequency-voltage relationship, thereby reducing the post-layout simulation time to 26% of the original circuits with the accuracy of 93%.