This paper proposes a test cost reduction method using machine learning techniques. The proposed method tries to predict good dies among the manufactured dies on the way of test process. If a die is predicted as good before completing all of the test process, the die will be allowed to be shipped without going through the remaining test process which contains costly burn-in test and final test. By a SVM-based procedure together with K-fold cross validation, a prediction model to judge certainly good dies is created from known results of the selected test items. In order to evaluate the method in terms of the business effectiveness, we also propose new evaluation measures, "cost reduction rate" and "bad die escape rate", which enable to confirm zero-defect oriented test cost reduction. Experimental results obtained through test data for industrial dies requiring zero-defect show that the proposed method has significant predictability with high test cost reduction capability.

In test of large scale integration (LSI) circuit, test escape is always regarded as a critical issue since significant cost is imposed to manufacturing cost. In this paper, we propose a novel outlier screening method for test escape. The proposed method exploits variational autoencoder (VAE) that is widely used to design complex generative model in artificial neural network field. While a typical autoencoder (AE) simply extracts features of training data, the VAE does it as probability distribution, and thus it can avoid potential risk of overfitting by using the probability distributions as a regularizer. Moreover, the proposed method effectively detects test escapes by utilizing the probability distributions as likelihood function of good chips. Through experiments using an industrial production test data, we demonstrate that the proposed method detects test escapes more than approximately 8.5 times as compared to that using a conventional AE-based method.

Studies of interactive systems in museums have raised important design considerations, but so far have failed to address sufficiently the particularities of family interaction and co-operation. This paper introduces qualitative video-based observations of Japanese families using an interactive portable guide system in a museum. Results show how unexpected usage can occur through particularities of interaction between family members. The paper highlights the necessity to more fully consider familial relationships in HCI.

Since the area ratio of SRAM occupied in SoC is over 60%, SRAMs usually share a BIST circuit. However, conventional shared BIST cannot perform at-speed test on a part of SRAM when it is shared by different address size SRAMs. We show a solution to this problem with slight extra area overhead and test time.

Numerous solutions have been proposed to reduce test data volume and test application time during manufacturing testing of digital devices. However, time to market challenge also requires a very efficient debug phase. Error identification in the test responses can become impractically slow in the debug phase due to large debug data, slow tester speed, and limited memory of the tester. In this paper, we investigate the problems and solutions related to using a relatively slow and limited memory tester to observe the at-speed behavior of fast circuits. Our method can identify all errors in at-speed scan BIST environment without any aliasing and using only little extra overhead by way of a multiplexer and masking circuit for diagnosis. Our solution takes into account the relatively slower speed of the tester and the reload time of the expected data to the tester memory due to limited tester memory while reducing the test/debug cost. Experimental results show that the test application time by our method can be reduced by a factor of 10 with very little hardware overhead to achieve such advantage.

Numerous solutions have been proposed to reduce test data volume and test application time during manufacturing testing of digital devices. However, time to market challenge also requires a very efficient debug phase. Error identification in the test responses can become impractically slow in the debug phase due to large debug data, slow tester speed and limited memory of the tester. In this paper, the authors investigate how a relatively slow and limited memory tester can observe the at-speed behavior of fast circuits. Our method can identify all errors in at-speed scan BIST environment without any aliasing and negligible extra hardware while taking into account the relatively slower speed of the tester and the re-load time of the expected data to the tester memory due to limited tester memory. Experimental results show that the test application time by our method can be reduced by a factor of 10 with very little hardware overhead to achieve such advantage

The object of this paper is to analyze the potential benefits of conducting a BIST pretest before launching a functional test of ICs during post manufacturing screening. In (Nakamura et al., 2005) the impact of BIST on the chip defect level after test has been addressed. It was assumed in (Nakamura et al., 2005) that no measures are taken to assure that the BIST circuitry is fault-free before launching the functional test. In this paper, we assume that a BIST pretest is first conducted in order to rid of all chips that fail it. Only chips whose BIST circuitry has passed the pretest are kept, while the rest are discarded. The BIST pretest, however, is assumed to have only a limited coverage against its own faults. This paper studies the product quality improvements as induced by the BIST pretest, and provides some insight as to when this pretest maybe worthwhile performing. As the study shows, in many cases the potential benefits outweigh any potential risks

This paper presents a card type battery-less information terminal $CardBIT - and a method of situated interaction that uses single-lens cameras. The CardBIT system provides situated information support at locations such as exhibition halls, train stations and streets. CardBIT can operate without a battery because it utilizes energy from the information car-tier and the user. It realizes location-and-direction-based interaction; a user can get appropriate information for his/her position and direction. The most significant feature of the CardBIT is its high portability because it is easily implanted into widely-used IC cards. Based on information accumulated in the CardBIT, personalized information in the form of sound, such as speech or music, is provided. Furthermore, a user can signal to the interface system and obtain information dynamically. This paper introduces the CardBIT system concept and its implementation using cameras, position estimation, and sign recognition methods. Our experiments show the feasibility of the proposed system.

This paper presents several design-for-testability (DFT) techniques for cell-based ICs. In the design of cell-based ICs, embedded cores are often used along with the user defined random logic. The existence of embedded cores makes chip level testing more difficult and complicated. Various test methods, such as test bus, internal and boundary scan, and BIST are selectively employed according to the target devices. The structures of those DFT methods being used for actual cell-based ASIC designs are described with their overhead in sample chips. How they are effectively integrated and automated is also explained.