Demo Data from EDBT 2026 / reviewers in the wild / expert
Paul M. Solomon
dblp:39/4432 · also Paul Michael Solomon
· DBLP profile ↗
4ranked-venue papers
0as first author
0since 2021 · last 2010
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Applied, interdisciplinary, general and emerging computing · 4Systems, architecture and hardware · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
3 papers |
Integrated circuit design · 89% Emerging computing paradigms · 7% Memory systems · 4% |
Topics — the 10 heaviest of 10, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Integrated circuit design
digital circuit design |
0.1 | 2 | 2010 | In Quest of the "Next Switch": Prospects for Greatly Reduced Power Dissipation in a Successor to the Silicon Field-Effect Transistor · Proc. IEEE 2010 Device scaling limits of Si MOSFETs and their application dependencies · Proc. IEEE 2001 |
Integrated circuit design
low-power circuit design |
0.1 | 2 | 2010 | In Quest of the "Next Switch": Prospects for Greatly Reduced Power Dissipation in a Successor to the Silicon Field-Effect Transistor · Proc. IEEE 2010 Device scaling limits of Si MOSFETs and their application dependencies · Proc. IEEE 2001 |
Integrated circuit design › semiconductor devices › device scaling
CMOS scaling limits |
0.1 | 2 | 2001 | Device scaling limits of Si MOSFETs and their application dependencies · Proc. IEEE 2001 Nanoscale CMOS · Proc. IEEE 1999 |
Emerging computing paradigms › nanoelectronics
nanoelectronic devices |
0.0 | 1 | 2010 | In Quest of the "Next Switch": Prospects for Greatly Reduced Power Dissipation in a Successor to the Silicon Field-Effect Transistor · Proc. IEEE 2010 |
Integrated circuit design › semiconductor device fabrication
CMOS technology |
0.0 | 1 | 1999 | Nanoscale CMOS · Proc. IEEE 1999 |
Integrated circuit design › semiconductor devices
device scaling |
0.0 | 1 | 1999 | Nanoscale CMOS · Proc. IEEE 1999 |
Integrated circuit design › semiconductor devices › MOS technology
nanoscale CMOS |
0.0 | 1 | 1999 | Nanoscale CMOS · Proc. IEEE 1999 |
Memory systems
DRAM |
0.0 | 1 | 2001 | Device scaling limits of Si MOSFETs and their application dependencies · Proc. IEEE 2001 |
Memory systems › random-access memory
SRAM |
0.0 | 1 | 2001 | Device scaling limits of Si MOSFETs and their application dependencies · Proc. IEEE 2001 |
Integrated circuit design › emerging device technologies
alternative device structures |
0.0 | 1 | 1999 | Nanoscale CMOS · Proc. IEEE 1999 |
Methods — techniques the papers use, named apart from their topics
device physics modeling · 0.2performance analysis · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2010 | In Quest of the "Next Switch": Prospects for Greatly Reduced Power Dissipation in a Successor to the Silicon Field-Effect TransistorabstractReduced power dissipation relative to the field-effect transistor (FET) is a key attribute that should be possessed by any device that has a chance of supplanting the FET as the ubiquitous building block for complex digital logic. We outline the possible physical approaches to achieving this attribute, and illustrate these approaches by citing current exploratory device research. We assess the value of the key exploratory research objectives of the semiconductor industry-sponsored Nanoelectronics Research Initiative (NRI) in the light of this pressing need to reduce dissipation in future digital logic devices. Thomas N. Theis, Paul M. Solomon |
Proc. IEEE | 2 |
| 2001 | Device scaling limits of Si MOSFETs and their application dependenciesabstractThis paper presents the current state of understanding of the factors that limit the continued scaling of Si complementary metal-oxide-semiconductor (CMOS) technology and provides an analysis of the ways in which application-related considerations enter into the determination of these limits. The physical origins of these limits are primarily in the tunneling currents, which leak through the various barriers in a MOS field-effect transistor (MOSFET) when it becomes very small, and in the thermally generated subthreshold currents. The dependence of these leakages on MOSFET geometry and structure is discussed along with design criteria for minimizing short-channel effects and other issues related to scaling. Scaling limits due to these leakage currents arise from application constraints related to power consumption and circuit functionality. We describe how these constraints work out for some of the most important application classes: dynamic random access memory (DRAM), static random access memory (SRAM), low-power portable devices, and moderate and high-performance CMOS logic. As a summary, we provide a table of our estimates of the scaling limits for various applications and device types. The end result is that there is no single end point for scaling, but that instead there are many end points, each optimally adapted to its particular applications. David J. Frank, Robert H. Dennard, Edward J. Nowak, Paul M. Solomon, Yuan Taur, H.-S. Philip Wong |
Proc. IEEE | 4 |
| 1999 | Nanoscale CMOSabstractThis paper examines the apparent limits, possible extensions, and applications of CMOS technology in the nanometer regime. Starting from device scaling theory and current industry projections, we analyze the achievable performance and possible limits of CMOS technology from the point of view of device physics, device technology, and power consumption. Various possible extensions to the basic logic and memory devices are reviewed, with emphasis on novel devices that are structurally distinct front conventional bulk CMOS logic and memory devices. Possible applications of nanoscale CMOS are examined, with a view to better defining the likely capabilities of future microelectronic systems. This analysis covers both data processing applications and nondata processing applications such as RF and imaging. Finally, we speculate on the future of CMOS for the coming 15-20 years. H.-S. Philip Wong, David J. Frank, Paul M. Solomon, Clement H. J. Wann, Jefferey J. Welser |
Proc. IEEE | 3 |
| 1997 | Supply and threshold voltage optimization for low power designabstractArticle Supply and threshold voltage optimization for low power design Share on Authors: David J. Frank IBM T.J. Watson Research Center, P.O. Box 218, Yorktown Heights, NY IBM T.J. Watson Research Center, P.O. Box 218, Yorktown Heights, NYView Profile , Paul Solomon IBM T.J. Watson Research Center, P.O. Box 218, Yorktown Heights, NY IBM T.J. Watson Research Center, P.O. Box 218, Yorktown Heights, NYView Profile , Scott Reynolds IBM T.J. Watson Research Center, P.O. Box 218, Yorktown Heights, NY IBM T.J. Watson Research Center, P.O. Box 218, Yorktown Heights, NYView Profile , John Shin Hyundai Electronics Industries, Korea Hyundai Electronics Industries, KoreaView Profile Authors Info & Claims ISLPED '97: Proceedings of the 1997 international symposium on Low power electronics and designAugust 1997 Pages 317–322https://doi.org/10.1145/263272.263364Online:01 August 1997Publication History 20citation343DownloadsMetricsTotal Citations20Total Downloads343Last 12 Months5Last 6 weeks1 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteGet Access David J. Frank, Paul M. Solomon, Scott K. Reynolds, John Shin |
ISLPED | 2 |