Distributed real-time computing is one of the enabling technologies in establishing a team of autonomous robots. A team of soccer playing robots, Paderkicker, contains many computing nodes handling environment perception, artificial intelligence, team coordination, autonomous actuation, and interactions with external entities such as a remote server. Robots must act with varying degrees of autonomy in real-time. The time-triggered message-triggered object (TMO) programming scheme offers a high-level high-precision approach to programming of distributed real-time computing operations. The TMO programmer can apply deadlines to method executions and result-arrivals in a straightforward way. He is thus relieved from dealing with low-level resource allocation details and can show considerably increased productivity. This paper describes a TMO structuring approach for constructing teams of autonomous robots. A TMO network architecture is described for the Paderkicker team.

We have integrated an image processing system built around PADDI-2, a custom 48 node MIMD parallel DSP. The system includes image processing algorithms, a graphical SFG tool, a simulator, routing tools, compilers, hardware configuration and debugging tools, application development libraries, and software implementations for hardware verification. The system board,connected to a SPARCstation via a custom Sbus controller, contains 384 processors in 8 VLSI chips. The software environment supports a multiprocessor system under development (VGI-1). The software tools and libraries are modular, with implementation dependencies isolated in layered encapsulations.

Performance of high-speed multiprocessor systems is limited by the available bandwidth to memory and the need to synchronize write sharable data. This paper presents a new memory system that separates synchronization related data from others. The memory system has two tiers: synchronization memory and high bandwidth (HB) memory. The synchronization memory consists of snooping caches connected to a bus and is used to store synchronization variables such as locks and semaphores. The HB memory is used to store the bulk of the application program code and data. It contains caches and a high bandwidth interconnection network to memory, such as the crossbar, but does not have full snooping among caches.The two tier memory system has been evaluated by analyzing the memory behavior of the simulated parallel execution of Prolog programs. Initial results indicate that the two tier memory system potentially reduces memory interference and speeds up synchronization. Three different schemes have been studied for the caches on the HB memory and the results are presented. The two-tier memory system has potential applications in areas where synchronization is light to medium and local data is often accessed.

An analysis of the Cray-1S architecture based on dataflow graphs is presented. The approach consists of representing the components of a Cray-1S system as the nodes of a dataflow graph and the interconnections between the components as the arcs of the dataflow graph. The elapsed time and the resources used in a component are represented by the attributes of the node corresponding to the component. The resulting dataflow graph model is simulated to obtain timing statistics using as input a control stream that represents the instruction and data stream of the real computer system.

The realization of multivalued combinational functions and sequential machines by using arrays of one type of cells is considered. The algebra used for the multivalued logic system has two binary operations and a set of unary operations. Each of these operations is realized by a cellular array. The cells are combinational and implemented by using binary logic gates. The cells are also designed so that all unrestricted multiple faults in arrays of these cells are detectable. Multivalued combinational functions, storage elements, and sequential machines are realized by interconnecting the arrays realizing the operations.

A semiconductor random-accessor memory (RAM) unit is a connection of RAM chips, data cable, chip select cable, and address cable so that each storage element can be selected for writing or reading independent of previous writes or reads. The faulty RAM unit is represented by a model consisting of four types of faults: stuck-at-0 or 1 fault on data cable, chip select cable, address cable, and storage elements in RAM chips, and a type of adjacent pattern interference fault in RAM chips. The testing of a RAM unit and locating faults to the RAM chips or wires in the various cables, when the RAM unit is part of a computer system, is considered. A set of six tests has been designed to diagnose the faults in the model. The sequence in which these tests have to be performed is determined. By using this sequence faulty components in a RAM unit are located when at most one type of fault in the model is present.

Fuzzy systems are multivalued logic with a continuum of truth values in [ 0,1]. If the truth values inthe interval [ 0,11 are quantized, the operations max (+) and min (*) can be physically realized. Precisely, if [ 0,1] is quantized into 2m equal intervals then the operation max (+) with n arguments can be realized by n rows of one-dimensional unilateral array, each having ( m + 1) cells. The cells in the array are combinational. The min (*) operation is realized by changing the boundary conditions to the array. Fuzzy forms are expressions of fuzzy variables using max (+) and min (*). These fuzzy forms are realized using the max (+) and min (*) gates.