John Knaizuk Jr.

dblp:39/4780 · DBLP profile ↗
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2ranked-venue papers
2as first author
0since 2021 · last 1977
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2 · 2 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
Electronic design automation · 87% Memory systems · 13%

Topics — the 3 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation › hardware verification and test
fault testing
0.021977
An Optimal Algorithm for Testing Stuck-at Faults in Random Access Memories · IEEE Trans. Computers 1977
An Algorithm for Testing Random Access Memories · IEEE Trans. Computers 1977
Electronic design automation › hardware verification and test › fault detection
stuck-at fault detection
0.021977
An Optimal Algorithm for Testing Stuck-at Faults in Random Access Memories · IEEE Trans. Computers 1977
An Algorithm for Testing Random Access Memories · IEEE Trans. Computers 1977
Memory systems
random-access memory
0.021977
An Optimal Algorithm for Testing Stuck-at Faults in Random Access Memories · IEEE Trans. Computers 1977
An Algorithm for Testing Random Access Memories · IEEE Trans. Computers 1977

Methods — techniques the papers use, named apart from their topics

test algorithm · 0.0
YearPublicationVenuePosition
1977 An Algorithm for Testing Random Access Memories
abstract
This correspondence presents an optimal algorithm to detect any single stuck-at-1 (s-a-1), stuck-at-0 (s-a-0) fault in a random access memory using only the n-bit memory address register input and m-bit memory buffer register input and output lines. It is shown that this algorithm requires 4 X 2nmemory accesses.
John Knaizuk Jr., Carlos R. P. Hartmann
IEEE Trans. Computers1
1977 An Optimal Algorithm for Testing Stuck-at Faults in Random Access Memories
abstract
This correspondence presents an optimal algorithm to detect any single "stuck-at-i," "stuck-at-O" fault and any combination of "stuck-at-I," "stuck-at-O" multiple faults in a random access memory using only the n-bit memory address register input and m-bit memory buffer register input and output lines. It is shown that this algorithm requires 4 X 2n memory accesses.
John Knaizuk Jr., Carlos R. P. Hartmann
IEEE Trans. Computers1