We present the design of a Sinc Cubed Decimator and of a Front End DSP Engine for Analog to Digital Conversion using high-level synthesis. The input language was SystemC and the High Level Synthesis tool was Cadence's C to Silicon compiler. Area and timing results, as well as comments on the overall experience, are also presented.

The paper describes a formal framework developed using the Prototype Verification System (PVS) to model and verify distributed simulation kernels based on the Time Warp paradigm. The intent is to provide a common formal base from which domain specific simulators can be modeled, verified, and developed. PVS constructs are developed to represent basic Time Warp constructs. Correctness conditions for Time Warp simulation are identified, describing causal ordering of event processing and correct rollback processing. The PVS theorem prover and type-check condition system are then used to verify all correctness conditions. In addition, the paper discusses the framework's reusability and extensibility properties in support of specification and verification of Time Warp extensions and optimizations.

Mixed-Mode simulation has been generating considerable interest in the simulation community and has continued to grow as an active research area. Traditional mixed-mode simulation involves the merging of digital and analog simulators in various ways. However, efficient methods for the synchronization between the two time domains remains elusive. This is due to the fact that the analog simulator uses dynamic time step control whereas the digital simulator uses the event driven paradigm. This paper proposes two new synchronization methods and presents their capabilities using a component-based continuous time simulator integrated with an optimistic parallel discrete event simulator. The results of the performance evaluation leads us to believe that while both synchronization methods are functionally viable, one has superior performance.