For high-level autonomous driving, the development of an effective vehicle-to-vehicle (V2V) communication system is an utmost concern. Among several candidates, the millimeter-wave (mmWave) V2V communication system is considered as a promising one, as it is expected to provide high data rate. To overcome the high path loss at mmWave frequencies, the codebook-based beam-alignment approach has been widely studied as a means of generating narrow and strong beams. Despite its potential, many existing codebooks are designed to generate codewords with equal beamwidths, which may not be optimal for V2V communications. Our focus is on designing a beamforming codebook for V2V communications, taking into account the angular distribution characteristics of vehicles on the road. To achieve this, we propose an analytical model to represent the traffic density of vehicles on roads. Based on the proposed traffic density model, we derive the angular distribution of directional communication links between vehicles by considering realistic road structures, including straight roads, intersections, and roundabouts. Utilizing the angular distribution between vehicles, we propose a codebook design framework specifically tailored for V2V communication systems. Simulation results verify that our model fits well for realistic urban grid road environments, and the proposed codebook outperforms codebooks with equal beamwidths.

We develop a vehicle motion state estimation algorithm based on an orthogonal frequency division multiplexing radar system suitable for vehicle-to-infrastructure (V2I) communications scenarios. Due to the transverse movement with respect to the direction from the target to roadside unit (RSU), the measured velocity is distorted as the Doppler shift depends on the angle formed between the vehicle position and RSU. To compensate for the distorted velocity, the exact vehicle position is required. However, this cannot be obtained in a system with a single RSU. In this paper, we develop an efficient cooperative vehicle state estimation algorithm that reduces the number of RSUs required for localization compared to conventional schemes by eliminating unnecessary RSUs to overcome the degradation of target detection performance in low signal-to-noise ratio regimes. Furthermore, the singularity problem due to the absence of Doppler shift when the vehicle travels near the tangential direction can be addressed with spatially distributed RSUs. Numerical results verify that the proposed estimation algorithm outperforms the existing schemes in V2I scenarios.

Matching the autonomous vehicle’s (AV) driving style to its user’s preference is core to a satisfactory user experience. The recent HCI community has undertaken a significant amount of research to understand user-preferred driving styles in AVs. Due to its multifaceted nature, understanding these driving preferences is difficult unless users take roles in an adaptive system and share their needs explicitly. However, there is a lack of a proper channel for users to express their driving-style needs in AVs. To bridge this gap, we suggest a user’s preferred driving-style guidance using voice as a novel input channel for human-centric AV control. We conducted a Wizard-of-Oz driving study on real roads, aiming to explore the guiding experience with the AV agent to reflect their driving-style preferences. This paper presents the value of driving-style guidance along with its burden to users, and concludes with its implications in designing a better AV-guiding experience.

We propose an efficient physics-based mixed-mode statistical simulation methodology for nanoscale devices and circuits. Here, 3-D Technology Computer Aided Design models pose a barrier for efficient simulation of variability as they generally involve millions of nodes in their mesh representations. The proposed methodology, which has been implemented for FinFET/tri-gate static random access memory (SRAM) design, overcomes this barrier by leveraging advanced physics-based 2-D (P2-D) devices with optimized meshes that are derived from 3-D FinFET models with tuned device parasitics. This enables physics-based simulation as well as physics-based variability input parameters. To improve accuracy, an embedded automated flow enables extraction of all external nodal parasitics, directly from a 3-D FinFET circuit layout representation. The circuits consisting of advanced P2-D devices are then back annotated with the nodal parasitics to enable fast and accurate SRAM dynamic margin mixed-mode simulations. Results demonstrate up to 200× speedup compared with traditional 3-D device simulations, and around five orders of magnitude wall clock time improvement on account of fast statistical methodologies, which are superior in comparison with traditional Monte Carlo analysis. This makes it feasible to supplant often inaccurate compact model-based simulations by true mixed-mode device simulations in statistical engines. The proposed physics-based methodology is also shown to corroborate well with hardware measurements.

Static Random Access Memories (SRAMs) are key components of modern VLSI designs and a major bottleneck to technology scaling as they use the smallest size devices with high sensitivity to manufacturing details. Analysis performed at the "schematic" level can be deceiving as it ignores the interdependence between the implementation layout and the resulting electrical performance. We present a computational framework, referred to as "Virtual SRAM Fab", for analyzing and estimating pre-Si SRAM array manufacturing yield considering both lithographic and electrical variations. The framework is being demonstrated for SRAM design/optimization in 45nm nodes and currently being used for both 32nm and 22nm technology nodes. The application and merit of the framework are illustrated using two different SRAM cells in a 45nm PD/SOI technology, which have been designed for similar stability/performance, but exhibit different parametric yields due to layout/lithographic variations. We also demonstrate the application of Virtual SRAM Fab for prediction of layout-induced imbalance in an 8T cell, which is a popular candidate for SRAM implementation in 32-22nm technology nodes.

Independent gate control in double-gate (DG) devices enhances circuit performance and robustness while substantially reducing leakage and chip area. In this paper, we describe circuit techniques which take advantage of the independent biasing properties of symmetrical and asymmetrical DG devices in design. DG circuits at the 25-nm node are analyzed via mixed-mode numerical simulations using Taurus MEDICI. In dynamic circuits, we give examples of conditional keepers, charge sharing prevention scheme, and static keepers. A conditional keeper can dynamically achieve the optimal strength ratio between keeper and evaluation devices by utilizing the front- and backchannel currents in DG devices. A charge sharing mitigation scheme utilizing the back-gate of a logic transistor is then described. Static data retention scheme in dynamic circuits is proposed. A case study for analog applications using a voltage controlled oscillator (VCO) illustrates the specific advantages of DG devices.

This paper presents a novel dynamic supply boosting technique for low voltage SRAMs at/beyond 65 nm PD/SOI technologies. For the first time the technique exploits the capacitive coupling effect in a floating-body PD/SOI device to dynamically boost the virtual array supply voltage during Read operation, thus improving the Read performance, Read/half-select stability, and Vmin. This enables significant reduction of the standby cell power and circuit active power in a single supply methodology. The performance and parametric yield improvements in the presence of variability are analyzed/validated using precise and fast Monte Carlo statistical circuit simulations with mixture importance sampling. Fabricated column-based 65nm PD/SOI SRAM circuits are confirmed with simulations and physical analysis and are shown to operate at 0.4 V. to 0.5V.

This paper demonstrates viable device design options for low-leakage and robust SRAM in sub-50nm FD/SOI technology. We explore the possibilities of reducing the body-doping of FD/SOI devices with proper tuning of back-gate bias or gate workfunction to achieve a given leakage target. The reduction of body-doping density helps reduce the effect of the random dopant fluctuation (RDF), while the Vt and leakage are controlled using the back-gate bias. Our analysis show that, body-doping reduction combined with back-gate biasing is the most efficient FD/SOI device design for low-leakage and robust SRAM.

This paper models and analyzes subthreshold and gate leakage currents in different double-gate (DG) devices, namely, a doped body symmetric device with polysilicon gates, an intrinsic body symmetric device with metal gates, and an intrinsic body asymmetric device with different front and back gate materials. The effect of variations in device parameters on the leakage components is also analyzed. Using the developed models, digital circuits (logic gates and static random access memory cells) designed with different DG structures are also analyzed. The analysis shows that the use of (near mid-gap) metal gate and intrinsic body devices significantly reduces both the total leakage and its sensitivity to parametric variations in DG devices and circuits

In this paper we model (numerically and analytically) and analyze sub-threshold, gate-to-channel tunneling, and edge direct tunneling leakage in Double Gate (DG) devices. We compare the leakage of different DG structures, namely, doped body symmetric device with polysilicon gates, intrinsic body symmetric device with metal gates and intrinsic body asymmetric device with different front and back gate material. It is observed that, use of (near-mid-gap) metal gate and intrinsic body devices significantly reduces both the total leakage and its sensitivity to parametric variations in DG circuits

Leakage power for extremely scaled (Leff = 25 nm) double-gate devices is examined. Numerical two-dimensional simulation results for double-gate CMOS device/circuit power are presented from physics principle, identifying that double-gate technology is an ideal candidate for low-power applications. Unique double-gate device features resulting from gate-gate coupling are discussed and effectively exploited for optimal low-leakage device design. Design trade-offs for double-gate CMOS power and performance are suggested for low-power and high-performance applications. Total power consumptions of static and dynamic circuits and latches for double-gate device are analyzed considering state dependency, showing that leakage current is reduced by a factor of over 10X, compared with conventional bulk-Si counterpart.

Static and dynamic power for strained-Si device is analyzed and compared with conventional bulk-Si technology. Optimum device design points are suggested with controlling physical/structural device parameters. Strained-Si CMOS circuits are studied, showing substantially-reduced power consumptions due to unique advantageous features of strained-Si device. The trade-offs for power and performance in strained-Si devices/circuits are discussed. Further, analysis and low-power design points are applied and extended to strained Si on SOI substrate (SSOI) CMOS technology.