This paper describes a family of high-speed Finite Impulse Response (FIR) digital filters that have been scaled across three generations of CMOS processes. The processes include commercial varieties as well as experimental bulk and low power Silicon-On-Insulator (SOI) technologies. Wafer tests demonstrate the speed and power advantages of the experimental SOI technology when applied to a 24 k-device digital signal processing (DSP) function, by direct comparison with the same filter manufactured in conventional (bulk) CMOS. The filters presented here have 8 taps and operate on 6 b data with 6 b programmable coefficients and deliver 12 b fixed-point output values, but the layout design is modular so that the number of taps and bits can be changed easily. The filters operate with maximal speeds of 250-600 MHz depending on the fabrication technology, and are suitable for the equalization task in Partial Response magnetic recording channels.

A guideline for scaling of CMOS technology for logic applications such as microprocessors is presented covering the next ten years, assuming that the lithography and base process development driven by DRAM continues on the same three-year cycle as in the past. This paper emphasizes the importance of optimizing the choice of power-supply voltage. Two CMOS device and voltage scaling scenarios are described. One optimized for highest speed and the other trading off speed improvement for much lower power. It is shown that the low power scenario is quite close to the original constant electric-field scaling theory. CMOS technologies ranging from 0.25 /spl mu/m channel length at 2.5 V down to sub-0.1 /spl mu/m at 1 V are presented and power density is compared for the two scenarios. Scaling of the threshold voltage along with the power supply voltage will lead to a substantial rise in standby power compared to active power and some tradeoffs of performance and/or changes in design methods must be made. Key technology elements and their impact on scaling are discussed. It is shown that a speed improvement of about 7/spl times/ and over two orders of magnitude improvement in power-delay product (mW/MIPS) are expected by scaling of bulk CMOS down to the sub-0.1 /spl mu/m regime as compared with today's high performance 0.6 /spl mu/m devices at 5 V. However, the power density rises by a factor of 4/spl times/ for the high-speed scenario. The status of the silicon-on-insulator (SOI) approach to scaled CMOS is also reviewed, showing the potential for about 3/spl times/ savings in power compared to the bulk case at the same speed.>